Techniques and Tools for Accelerating Low Power Design Simulations

Techniques and Tools for Accelerating Low Power Design Simulations
by Kalar Rajendiran on 02-17-2021 at 10:00 am

Figure 1 for Synopsys Blog

I recently watched a webinar titled “How to accelerate power-aware simulation debug with Synopsys’ VC LP” that was presented by Ashwani Kumar Dwivedi senior applications engineer at Synopsys. Watching the webinar made me reminisce how design verification has evolved over the years. A long time ago, static verification started… Read More