"Re-Inventing" Tapeout Sign-off — Applying Big Data Techniques to Electrical Analysis

"Re-Inventing" Tapeout Sign-off — Applying Big Data Techniques to Electrical Analysis
by Tom Dillinger on 05-23-2016 at 7:00 am

A common SoC design methodology in current use starts with preparation of the physical floorplan — e.g., block/pin placement, global clock domain and bus signal planning, developing the global/local power distribution (and dynamic power domain management techniques). Decoupling capacitor estimated densities and… Read More