DDR4 is a complex interface to verify — assistance needed!

DDR4 is a complex interface to verify — assistance needed!
by Tom Dillinger on 02-16-2016 at 7:00 am

The design of parallel interfaces is supposed to be (comparatively) easy — e.g., follow a few printed circuit board routing guidelines; pay attention to data/clock/strobe signal lengths and shielding; ensure good current return paths (avoid discontinuities); match the terminating resistances to the PCB trace impedance;… Read More