Mentor Cuts Circuit Verification Time with Unique Recon Technology

Mentor Cuts Circuit Verification Time with Unique Recon Technology
by Mike Gianfagna on 07-17-2020 at 6:00 am

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Most of us will remember the productivity boost that hierarchical analysis provided vs. analyzing a chip flat. This “divide and conquer” approach has worked well for all kinds of designs for many years. But, as technology advances tend to do, the bar is moving again. The new challenges are rooted in the iterative nature of high complexity… Read More


DRC/DFM inside of Place and Route

DRC/DFM inside of Place and Route
by Daniel Payne on 03-31-2011 at 10:19 am

Intro
Earlier this month I drove to Mentor Graphics in Wilsonville, Oregon and spoke with Michael Buehler-Garcia, Director of Marketing and Nancy Nguyen, TME, both part of the Calibre Design to Silicon Division. I’m a big fan of correct-by-construction thinking in EDA tools and what they had to say immediately caught my… Read More