I first heard about High Level Synthesis (HLS) while working in EDA at Viewlogic back in the 1990s, and have kept watch on the trends over the past decades. Earlier this year Siemens EDA hosted a two day event, having speakers from well-known companies share their experiences about using HLS and High Level Verification (HLV) in their… Read More
Webinar: Turning Shift-Left from Slogan to Reality
SoC teams are routinely told to “shift left”—to find design and verification problems earlier, where they are cheaper to fix—yet in most flows the first model that is both performance-accurate and authoritative is still the RTL, which arrives late and simulates slowly. This webinar will show that SystemC models built with the