As architects push toward advanced nodes and increasingly demanding workloads, modern silicon design has entered an era of unprecedented complexity. A single design respin can cost millions of dollars and delay market entry. Against this backdrop, designs must be balanced for performance, bandwidth, power efficiency, security… Read More
Daniel is joined by Robert Kruger, product management director at Synopsys, where he oversees IP solutions for multi-die designs, including 2D, 3D, and 3.5D topologies. Throughout his career, Robert has held key roles in product marketing, business development, and roadmap planning at leading companies such as Intel, Broadcom,… Read More
As I mentioned in a previous blog Cadence Update 2012, Martin Lund is now in charge of the Cadence IP strategy. Martin read my first blog and wanted to exchange IP strategies so we met at DAC 2012 for a chat. Not only did Martin connect with me on LinkedIn, he also joined the SemiWiki LinkedIn group, which now has 4,000+ members. So yes,… Read More
