How to meet 3Ps in 3D-ICs with sub-20nm Dies?

How to meet 3Ps in 3D-ICs with sub-20nm Dies?
by Pawan Fangaria on 03-06-2014 at 1:30 am

It feels to be at the top of semiconductor technology by having dies with high density of semiconductor design at sub-20nm technology node stacked together into a 3D-IC to form a complete SoC which can accommodate billions of gates. However there are multiple factors to be looked at in order to make that successful amid often conflicting… Read More