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Custom Layout Productivity Gets a Boostby Tom Dillinger on 04-11-2016 at 7:00 amCategories: EDA, Synopsys
In the 1970’s, when Moore’s Law was still in its infancy, Bill Lattin from Intel published a landmark paper [1]. In it he identified the need for new design tools and methods to improve layout productivity, which he defined as the drawn and verified number of transistors per day per layout designer. He said existing … Read More