For many years TSMC has provided IC design implementation guidance as viewed from the process and manufacturing standpoints. The last time TSMC Reference Flow incremented, it was version 12.0 back in 2011. Since then, increased design, process and packaging related complexities of the advanced nodes have demanded more focused… Read More
Pipelining exploits parallelism of sub-processes with intent to achieve a performance gain that otherwise is not possible. A design technique initially embraced at the CPU micro-architectural level, it is achieved by overlapping the execution of previously segregated processor instructions –commonly referred … Read More
Earlier physical optimization impacts a design QoR gain and can disclose potential hurdles in dealing with unknown design variants such as new IP inclusion or new process node issues. Along the RTL-to-GDS2 implementation continuum, a left-shift move requires a robust modeling and proper context captures in order to produce… Read More
One of the biggest surprises at the TSMC OIP Forum last week was the reappearance of bankrupt EDA vendor ATopTech. I spoke with former ATopTech CEO and now Avatar IS President Jue-Hsien Chern at OIP. As a survivor of several EDA legal battles myself, I understand what ATopTech went through and I am thoroughly impressed that they had… Read More
