Sidense overlays OTP on TSMC 16nm FinFET

Sidense overlays OTP on TSMC 16nm FinFET
by Don Dingee on 09-13-2014 at 7:00 am

Process shrinks, which have served us well for most of the Moore’s Law journey, are reaching their limits. For switching transistors, the biggest problems of leakage current and gate oxide vulnerability in planar MOSFETs have led the industry to new 3D microstructures such as FinFET. For non-volatile memory, the problem is generally… Read More