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B
I also note the data is 2-3 years old, in other words before anyone has any experience with trying to actually put high-NA into volume...
Jun 18, 2026
B
Intel says you don't need Double Patterning for 0.55NA 24nm pitch
Jun 18, 2026
B
Indeed -- but my point was that in N2 TSMC *already* have a smaller M0 pitch than single-exposure high-NA can deliver, as you said: "No...
Jun 18, 2026
No of course you can't -- all I was saying is that chip pricing matters more at the low end, at the high end you can charge more to...
Jun 18, 2026
Intel will probably need fewer units, but the challenges of cost and throughput may not be any less—if not greater. For example...
Jun 18, 2026
S
One other important consideration for high NA is stitching. I don't think Intel can skirt around it. The High-NA scanner's throughput...
Jun 18, 2026
S
FYI: I was told privately by a trusted source that these numbers are not correct. The correct numbers are under strict NDA which I will...
Jun 18, 2026
F
One other important consideration for high NA is stitching. I don't think Intel can skirt around it. The High-NA scanner's throughput...
Jun 18, 2026
F
TSMC notes from SPIE:
High-NA EUV remains challenged in yield as stochastic defect makes high-NA EUV linewidth roughness even harder to...
Jun 18, 2026
FYI: I was told privately by a trusted source that these numbers are not correct. The correct numbers are under strict NDA which I will...
Jun 18, 2026
TSMC notes from SPIE:
High-NA EUV remains challenged in yield as stochastic defect makes high-NA EUV linewidth roughness even harder to...
Jun 18, 2026
I
So it's deceptive to post it as if it shows a usability comparison between high-NA and SALELE low-NA, because it would lead people to...
Jun 18, 2026
F
It was a measure of confidence against "variability risk", the "variability" not being stochastics, but process steps, e.g., overlay...
Jun 18, 2026