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F
TSMC notes from SPIE:
High-NA EUV remains challenged in yield as stochastic defect makes high-NA EUV linewidth roughness even harder to...
Jun 18, 2026
FYI: I was told privately by a trusted source that these numbers are not correct. The correct numbers are under strict NDA which I will...
Jun 18, 2026
TSMC notes from SPIE:
High-NA EUV remains challenged in yield as stochastic defect makes high-NA EUV linewidth roughness even harder to...
Jun 18, 2026
I
So it's deceptive to post it as if it shows a usability comparison between high-NA and SALELE low-NA, because it would lead people to...
Jun 18, 2026
F
It was a measure of confidence against "variability risk", the "variability" not being stochastics, but process steps, e.g., overlay...
Jun 18, 2026
I
So in that case 20nm-24nm is not "green" for high-NA, contrary to what the slide suggests?
Jun 18, 2026
F
Intel had the tool since 2024 and i doubt Intel is dumb enough to do 10nm again they won't survive another 10nm...
Jun 18, 2026
F
So I went through the whole presentation just now. I am not sure why only one slide was posted originally by someone to make some...
Jun 18, 2026
I
oops my bad i misread that
Jun 18, 2026
S
oops my bad i misread that
Jun 18, 2026
I
I didn't say the price hike was 100%, I said that a price hike (of whatever size) was 100% certain to happen, compared to a much smaller...
Jun 18, 2026
S
agreed.
I think the assumption of 100% price increase of the chip is the problem and AMD has said the price is roughly 5-15% higher in...
Jun 18, 2026
I
No of course you can't -- all I was saying is that chip pricing matters more at the low end, at the high end you can charge more to...
Jun 18, 2026
S
at the top end of product can you justify having delays ? a 150-160mm2 chip would be better than a 400-500mm2 Chip for doing...
Jun 18, 2026