Array
(
[content] =>
[params] => Array
(
[0] => /forum/whats-new/latest-activity?before_id=114273
)
[addOns] => Array
(
[DL6/MLTP] => 13
[Hampel/TimeZoneDebug] => 1000070
[SV/ChangePostDate] => 2010200
[SemiWiki/EmailDomainReplace] => 1000010
[SemiWiki/Newsletter] => 1000010
[SemiWiki/WPMenu] => 1000010
[SemiWiki/XPressExtend] => 1000010
[ThemeHouse/XLink] => 1000970
[ThemeHouse/XPress] => 1010570
[XF] => 2031070
[XFI] => 1060170
)
[wordpress] => /var/www/html
)
You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please,
join our community today !
JavaScript is disabled. For a better experience, please enable JavaScript in your browser before proceeding.
You are using an out of date browser. It may not display this or other websites correctly.
You should upgrade or use an
alternative browser .
F
I also note the data is 2-3 years old, in other words before anyone has any experience with trying to actually put high-NA into volume...
Jun 18, 2026
I
I also note the data is 2-3 years old, in other words before anyone has any experience with trying to actually put high-NA into volume...
Jun 18, 2026
F
Intel had the "confidence", from earlier (see the source years).
Jun 18, 2026
F
Well wait, the SALELE is more extendible?
Jun 18, 2026
I
So guess what N2 is... ;-)
(I didn't want to give an exact number because of NDA...)
P.S. N2P is ~0.5um smaller due to 2% linear...
Jun 18, 2026
I
Who's right then -- Intel or Fred? ;-)
Jun 18, 2026
S
Intel says you don't need Double Patterning for 0.55NA 24nm pitch
Jun 18, 2026
S
M0 for N3E is 23nm
Jun 18, 2026
I
Indeed, this must have gone thru TSMC's thinking, perhaps Samsung too?
Jun 18, 2026
F
Indeed, this must have gone thru TSMC's thinking, perhaps Samsung too?
Jun 18, 2026
F
Indeed -- but my point was that in N2 TSMC *already* have a smaller M0 pitch than single-exposure high-NA can deliver, as you said: "No...
Jun 18, 2026
I
Indeed -- but my point was that in N2 TSMC *already* have a smaller M0 pitch than single-exposure high-NA can deliver, as you said: "No...
Jun 18, 2026
F
I recall TSMC already had 28 nm pitch M0 for N5P.
Jun 18, 2026
I
Surely the biggest issue with TSMC adopting high-NA is not just the economics/throughput, but the sheer number of machines that would be...
Jun 18, 2026
I
M0 pitch in TSMC N2 is less than 24nm... ;-)
Jun 18, 2026
