Array
(
[content] =>
[params] => Array
(
[0] => /forum/whats-new/latest-activity?before_id=103648
)
[addOns] => Array
(
[DL6/MLTP] => 13
[Hampel/TimeZoneDebug] => 1000070
[SV/ChangePostDate] => 2010200
[SemiWiki/Newsletter] => 1000010
[SemiWiki/WPMenu] => 1000010
[SemiWiki/XPressExtend] => 1000010
[ThemeHouse/XLink] => 1000970
[ThemeHouse/XPress] => 1010570
[XF] => 2030770
[XFI] => 1060170
)
[wordpress] => /var/www/html
)
You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please,
join our community today !
JavaScript is disabled. For a better experience, please enable JavaScript in your browser before proceeding.
You are using an out of date browser. It may not display this or other websites correctly.
You should upgrade or use an
alternative browser .
M
Part of the long lists of mountains to climb for TSMC Arizona, is to set up suppliers for all their plant infrastructure as well as when...
Dec 21, 2025
J
Yes, at least 2 EXE:5000 development systems are in Oregon and the EXE:5200 production system is mostly likely there too.
The HNA field...
Dec 21, 2025
J
Intel got the first EXE:5000, that is a development machine and they received at least one more EXE:5000. Now they are starting to get...
Dec 21, 2025
M
Really? Intel's integrated CPU graphics are arguably the world's highest volume production graphics. Datacenter and supercomputing...
Dec 21, 2025
What does dominance mean?
Would TSMC have done Strained Silicon, Gate Last, FinFET, Nanosheet, or Backside if Intel hadn't. TSMC has...
Dec 21, 2025
Do you know if NVMe / PCI Express was also a limiting factor in Optane's performance in storage applications? I always got the sense...
Dec 21, 2025
Really? Intel's integrated CPU graphics are arguably the world's highest volume production graphics. Datacenter and supercomputing...
Dec 21, 2025
S
Are you talking about this?: "Chandrasekaran told CNBC that Fab52 is capable of more than 10,000 18A wafer starts per week."
Capable has...
Dec 21, 2025
C
I have been saying on this forum from some time that China would catch up on EUV and the industry seconds source will not be Intel but...
Dec 21, 2025
T
Good responses btw.
For LBT + 14A, I understand why he did it (and he may have had no choice), but it also rings a bit as 'shooting...
Dec 21, 2025
S
What does dominance mean?
Would TSMC have done Strained Silicon, Gate Last, FinFET, Nanosheet, or Backside if Intel hadn't. TSMC has...
Dec 21, 2025
S
20K of N4 and smaller amount of N3, wow GO AMERICA lots of capacity to support Apple, Nvidia, AMD, Qualcomm. That will be less than...
Dec 21, 2025
S
Intel needs more wafer starts plain and simple, either external customers or internal pulling more wafer starts back from the other...
Dec 21, 2025
20K of N4 and smaller amount of N3, wow GO AMERICA lots of capacity to support Apple, Nvidia, AMD, Qualcomm. That will be less than...
Dec 21, 2025
20K of N4 and smaller amount of N3, wow GO AMERICA lots of capacity to support Apple, Nvidia, AMD, Qualcomm. That will be less than...
Dec 21, 2025