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The 19th System Level Interconnect Prediction 2017 workshop

Daniel Payne

Moderator
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Co-sponsored by the ACM SIGDA and the IEEE Computer Society




June 17, 2017




Co-located with the 54th Design Automation Conference, June 18-22, 2017.

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website: SLIP online


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** Deadline EXTENDED to Apr. 1st, 2017 **


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** Selected papers will be invited to the special issue of Integration, the VLSI Journal **
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Selected papers will be invited to the special issue titled "Emerging Technologies for System Level Design and Interconnects" in Integration, The VLSI Journal


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** Resources for Students Provided by the TCVLSI from IEEE Computer Society **
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SLIP 2017 will be giving two student travel grants and one best student paper award. For more information, please visit our website: SLIP online


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** Call for Submission **


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The general technical scope of the workshop is the design, analysis, prediction, and optimization of interconnect and communication fabrics in electronic systems. The organizing committee invites original contributions to the workshop. These contributions include papers, tutorials, panels, special sessions, and posters. We accept papers based on novelty and contributions to the advancement of the field. The accepted papers will be published in the ACM and IEEE digital libraries.




Technical topics include but are not limited to:


? Interconnect prediction and optimization at various IC and system design stages


? System-level design for FPGAs, NOCs, reconfigurable systems


? Design, analysis, and optimization of power and clock networks Interconnect reliability Interconnect topologies and fabrics of multi- and many-core architectures


? Design-for-manufacturing (DFM) and yield techniques for interconnects


? High speed chip-to-chip interconnect design


? Design and analysis of chip-package interfaces


? Power consumption of interconnects


? 3D interconnect design and prediction


? Emerging interconnect technologies


? Applications of interconnects to social, genetic, and biological systems


? Co-optimization of interconnect technology and chip design






Submission:


We invite authors to submit papers of 4 to 8 pages, double-columned, 9pt or 10pt font in ACM proceedings format available at www.acm.org/sigs/publications/proceedings-templates




To permit double blind review, all papers must remove author information (submissions with author information will be rejected). Authors should submit papers electronically:


Log in to EasyChair for SLIP17


(New) Student Awards:


Provided by the IEEE Computer Society’s Technical Committee on VLSI (TCVLSI), the Best Student Paper Award will be awarded for a SLIP2017 paper whose first author is a student. In addition, limited student travel grants of $250 are available. Details will follow on the website.






Format:


The workshop includes keynotes, regular paper sessions, interactive panels, tutorials, invited talks, and interactive poster sessions. Our program also includes lunch, refreshments, and a traditional social dinner with fun elements.


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Important Dates:


Abstract Registration: Mar 11, 2017


Paper Submission: Mar 18, 2017 EXTENDED to Apr 1, 2017


Author Notification: April 22, 2017


Final Version Upload: May 1, 2017


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General Chair: Tsung-Yi Ho, National Tsing Hua Univ., TW


Technical Program Chair: Shiyan Hu, Michigan Tech., USA


Technical Program Co-Chair: Mustafa Badaroglu, Qualcomm Inc., USA


Finance Chair: Amlan Ganguly, Rochester Inst. of Technology, USA


Publicity Chair: Cheng Zhuo, Zhejiang Univ., P.R. China


Panel Chair: Yanzhi Wang, University of Syracuse, USA


Publications Chair: Selcuk Kose, University of South Florida, USA






For questions, contact Tsung-Yi Ho < tyho@cs.nthu.edu.tw >
 
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