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Parallel Circuit Simulator - Xyce Version 6.2 released

Daniel Payne

Moderator
View attachment 12302
The Xyce (TM) team is pleased to announce the release of Xyce (TM)
Version 6.2. This release is a minor release that fixes a number of
bugs in Xyce (TM) 6.1 and includes improvements to existing features
of Xyce (TM) 6.1. Please see the Release Notes for a complete list of
new features and enhancements.


Highlights for Xyce Release 6.2 include:


* Calculation of transient direct sensitivities.
* Support for lead current calculation and output for Harmonic
Balance (HB) analysis.
* Improved interpolation for both the Trapezoid and Gear time
integrators.
* Improved results output (.PRINT) capabilities.
* New models for a lumped transmission line and a digital latch.
* Fixes for nearly 60 bugs and enhancement requests.


For details, see the Xyce(TM) Users' Guide and the Xyce(TM) Reference
Guide.


Also associated with this release are updates to the web site. The
Frequently Asked Questions page and the instructions for adding device
models to Xyce(TM) through Verilog-A have been updated.


To obtain a copy of Xyce(TM) Release Version 6.2, please see the
downloads section of the web site: http://xyce.sandia.gov/downloads




The team actively participates in an open forum for discussion of Xyce
on Google Groups. Details on how to join this forum are on the
Documentation and Tutorials page of the web site,
http://xyce.sandia.gov/documentation/index.html.


Thank You,
The Xyce(TM) Team
 
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