MemCon 2015 Presentations Now Available!

[Daniel Nenni]

MemCon, the memory industry’s premier technical and ecosystem event, showcases the thought leaders driving advances in memory technology. Targeting decision makers and innovators in memory, systems integration, IP development, semiconductor design, and SoC development, MemCon offers insights into advanced technologies and standards and opportunities to network with leaders.

It was a very interesting conference and now you can browse through the slides:

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| valign="top" style="border-collapse: collapse; border: 1px solid #ccc" |
| align="center" valign="top" width="21%" style="border-collapse: collapse; border: 1px solid #ccc; background: #eee" | Track 1
Market Trends
| align="center" valign="top" width="21%" style="border-collapse: collapse; border: 1px solid #ccc; background: #fff" | Track 2
Mainstream Memory
| align="center" valign="top" width="21%" style="border-collapse: collapse; border: 1px solid #ccc; background: #eee" | Track 3
System & Architecture
| align="center" valign="top" width="23%" style="border-collapse: collapse; border: 1px solid #ccc; background: #eee" | Track 4
Today's Technologies
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| valign="top" style="border-collapse: collapse; border: 1px solid #ccc" | 1:00pm-1:45pm
| valign="top" style="border-collapse: collapse; border: 1px solid #ccc; background: #eee" | MKT101
The 3rd Wave: Hyper Performance and the End of Commodity Memory
Tezzaron

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| valign="top" style="border-collapse: collapse; border: 1px solid #ccc; background: #fff" | MSM101
Graphics Memory for Networking? - A Bandwidth Band-aid or Breakthrough?
Micron

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| valign="top" style="border-collapse: collapse; border: 1px solid #ccc; background: #eee" | SAT101
Complexities in Developing a High Performance DDR Subsystem at 3200 Mbps on 16FF+ and 10FF
Cadence

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| valign="top" style="border-collapse: collapse; border: 1px solid #ccc; background: #fff" | TDT101
Serial Memories Fill A Need
MoSys

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| valign="top" style="border-collapse: collapse; border: 1px solid #ccc" | 1:50pm-2:35pm
| valign="top" style="border-collapse: collapse; border: 1px solid #ccc; background: #eee" | MKT102
How NAND Flash Threatens DRAM
Objective Analysis

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| valign="top" style="border-collapse: collapse; border: 1px solid #ccc; background: #fff" | MSM102
LPDDR3/4-ECC DRAM for High-reliability IoT, Automotive and Control System Applications
Green Mountain

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| valign="top" style="border-collapse: collapse; border: 1px solid #ccc; background: #eee" | SAT102
Navigating DDR4 and LPDDR4 Trace Captures and Eye Scans for System Debug and Validation
Keysight Technologies

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| valign="top" style="border-collapse: collapse; border: 1px solid #ccc; background: #fff" | TDT102
xFD For High-density DDR4 RDIMM Module Applications
Invensas

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| valign="top" style="border-collapse: collapse; border: 1px solid #ccc" | 2:40pm-3:25pm
| valign="top" style="border-collapse: collapse; border: 1px solid #ccc; background: #eee" | MKT103
Towards a Heterogeneous Memory Channel with Hybrid Modules
JEDEC

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| valign="top" style="border-collapse: collapse; border: 1px solid #ccc; background: #fff" | MSM103
How to Efficiently Design and Analyze a DDR4 Interface
Cadence

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| valign="top" style="border-collapse: collapse; border: 1px solid #ccc; background: #eee" | SAT103
Performance Optimizations for Mobile Memory Sub-*Systems
ARM

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| valign="top" style="border-collapse: collapse; border: 1px solid #ccc; background: #fff" | TDT103
High Speed High Density and Low Power TCAM
CMOS Micro Device Inc

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| valign="top" style="border-collapse: collapse; border: 1px solid #ccc" | 3:30pm-4:00pm
| colspan="4" align="center" valign="top" style="border-collapse: collapse; border: 1px solid #ccc; background: #eee" | AFTERNOON BREAK / EXHIBIT HALL
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| valign="top" style="border-collapse: collapse; border: 1px solid #ccc" | 4:00pm-4:45pm
| valign="top" style="border-collapse: collapse; border: 1px solid #ccc; background: #eee" | MKT104
Memory Technologies and Ecosystem for the Emerging IoT Market
TSMC
| valign="top" style="border-collapse: collapse; border: 1px solid #ccc; background: #fff" | MSM104
Intelligent Modules and Scalable Infrastructures for Verification Automation
SolarAsic

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| valign="top" style="border-collapse: collapse; border: 1px solid #ccc; background: #eee" | SAT104
Row Hammer Failures in DDR Memory
FuturePlus

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| valign="top" style="border-collapse: collapse; border: 1px solid #ccc; background: #fff" | TDT104
Memory Solutions for High Performance Computing
Altera

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| valign="top" style="border-collapse: collapse; border: 1px solid #ccc" | 4:50pm-5:35pm
| valign="top" style="border-collapse: collapse; border: 1px solid #ccc; background: #eee" | MKT105
TSV based Memory Solutions Engaging in IoT & IoE Trend
SK Hynix

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| valign="top" style="border-collapse: collapse; border: 1px solid #ccc; background: #fff" | MSM105
New Hardware to Increase Server Memory Capacity for In-memory Computing and Big Data
Synopsys

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| valign="top" style="border-collapse: collapse; border: 1px solid #ccc; background: #eee" | SAT105
Using the On-Chip Network to Optimize Multi-Channel DRAM Throughput
Sonics

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| valign="top" style="border-collapse: collapse; border: 1px solid #ccc; background: #fff" | TDT105
Validating an LPDDR4 Memory Interface with Multiple Frequencies and Gated Clock Intervals
Nexus Technology

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