Low-Power Technology Summit

[Daniel Nenni]

[FONT=Arial, Helvetica, sans-serif]Join Cadence on October 18 for our Low-Power Technology Summit. Experts from Cadence and other leading companies will present the latest low-power design methodologies. Find out how they applied new techniques to meet their aggressive project goals.


The Summit is also a great opportunity to ask questions and network with industry experts. Whether your challenge is verification, physical implementation, or signoff, the Summit will give you a new perspective on improving your low-power flow and your overall productivity.

[h=3]Time & Date[/h] Thursday, Oct. 18, 2012
8:30am - 5:00pm
[h=3]Location[/h] Cadence Design Systems, Bldg. 10 auditorium, San Jose, CA
Register now! Cadence Events & Webinars
[h=3]Agenda[/h]

• 08:30am-09:15am Registration
• 09:15am-09:30am Welcome by Cadence Executive
• 09:30am-10:30am Keynote Presentation: Professor Jan Rabaey, UC Berkeley
• 10:30am-10:45am Coffee break
• 10:45am-11:30am Low-Power Solution Technology Update, Cadence
• 11:30am-12:30pm Low-Power Design with ARM® Physical IP and Processor Optimization Packs, ARM
• 12:30pm-01:30pm Lunch with R&D roundtable
• 01:30pm-02:15pm Low Power Verification in Mixed-Signal Designs, Cadence
• 02:15pm-03:00pm Customer Case Study: Low-Power Design Experiences on Kinetis, Freescale
• 03:00pm-03:15pm Coffee break
• 03:15pm-04:00pm Power Format Standards Update, Dr. Qi Wang, Cadence
• 04:00pm-04:45pm Panel Discussion and Q&A
• 04:45pm-05:00pm Prize Draw & Close

Register now – we look forward to seeing you! Cadence Events & Webinars

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