Array
(
    [content] => 
    [params] => Array
        (
            [0] => /forum/threads/design-and-verification-conference-exhibition-india.4612/
        )

    [addOns] => Array
        (
            [DL6/MLTP] => 13
            [Hampel/TimeZoneDebug] => 1000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000970
            [ThemeHouse/XPress] => 1010570
            [XF] => 2021770
            [XFI] => 1050270
        )

    [wordpress] => /var/www/html
)

Design and Verification Conference & Exhibition INDIA

Pawan Fangaria

New member
The Design and Verification Conference & Exhibition INDIA is nearing its schedule on 25-26 September 2014 at Hotel Park Plaza in Bangalore, INDIA.

Discounted early bird registration has been extended till September 8, Register here.

Have a look at the detailed program at a glance here.

There are important Keynote Speeches by industry veterans –

Wally Rhines, CEO, Mentor Graphics – “Accelerating EDA Innovation Through SoC Design Methodology Convergence

Mahesh Mehendale, CTO, MCU, Texas Instruments – “Challenges in the design and verification of ultra-low power “more than Moore” systems

There are exciting Invited Talks by industry leaders –

Martin Vaupel, Robert Bosch – “Virtual Prototypes in Automotive from a Tier1 Perspective: Use Cases, Requirements and Challenges

Others TBD

There are many tutorials on interesting topics in ESL and Design Verification -

1. Power Aware Architecture Definition and Software Development using Virtual Prototypes
2. SystemC AMS based methodologies for the design and verification of heterogeneous systems
3. Virtual Prototyping Methodologies, Applications, and a Case Study in Embedded System Development for a Motor Control Application with Fault Injection Analysis
4. Low Power Design & Verification Using High-Level Synthesis
5. Easier UVM – Making Verification Methodology more Productive
6. Achieving Portable Stimulus with Graph-Based Verification
7. SoC Verification Challenges Offer Opportunities to Take a New Look at Debug
8. SystemVerilog for Design

Technical Tracks with conference papers on cutting-edge technologies in ESL and Design Verification –

Several papers will be presented within separate tracks on UVM, ESL, AMS, ABV FORMAL, CDC, X-CHECK, EMU, PROTOTYPING, PRE-SI CHARACTERIZATION, LOW POWER/POWER AWARE, DEBUG, IP-2-SoC REUSE, and several other selected topics.

To review everything about this conference and more insight into papers, several videos, exhibitions etc. navigate through its website.
 
Back
Top