Announcing the 23[SUP]rd[/SUP] Annual Electronic Design Process Symposium & Cyber Security Workshop
April 21 & 22, 2016
Monterey Tides Hotel, Monterey, CA
Sponsored by:
IEEE Computer Society of Silicon Valley (CS-SCV)
Design Automation Technical Committee (DATC)
Council on Electronic Design Automation (CEDA)
The Electronic Design Processes Symposium (EDPS) provides a forum for a cross-section of the top thinkers, movers, and shakers who focus on how chips and systems are designed, and to discuss state-of-the-art electronic design processes and CAD methodologies. The symposium focuses on the improvement of the overall design process, rather than on the functions of the individual tools themselves.
EDPS Home Page[table] align="right" border="1" style="width: 313px"
|-
| colspan="2" style="height: 26px; width: 313px" | 2016 Keynote Speakers
|-
| style="height: 26px; width: 139px" | Ken Caviasca
| style="height: 26px; width: 174px" | VP, R&D, Intel
|-
| style="height: 26px; width: 139px" | Serge Leef
| style="height: 26px; width: 174px" | GM, Mentor Graphics
|-
| style="height: 26px; width: 139px" | Cmdr. Chris Eagle
| style="height: 26px; width: 174px" | Sr. Lecturer, Naval Post Graduate School
|-
[/table]
Thursday 4/21 Session Themes:
Friday 4/22 Security Day & Workshop:
Authors should submit full-length, original, and unpublished abstracts, presentations & posters along with author’s contact information. Proposals for special, poster, and panel sessions may also be submitted; a one-page description along with organizer’s contact information is required. Send presentations, and proposals to: edps-committee@googlegroups.com with “2016 proposed paper” in the Subject: line.
[table] align="right" border="1"
|-
| colspan="2" style="height: 10px; width: 288px" | Sample of Companies
Present in 2015:
|-
| style="height: 10px; width: 152px" | Oracle
| style="height: 10px; width: 136px" | Cadence
|-
| style="height: 10px; width: 152px" | Samsung
| style="height: 10px; width: 136px" | Stanford Univ.
|-
| style="height: 10px; width: 152px" | ASE
| style="height: 10px; width: 136px" | Synapse
|-
| style="height: 10px; width: 152px" | Mentor
| style="height: 10px; width: 136px" | Synopsys
|-
| style="height: 10px; width: 152px" | Global Foundries
| style="height: 10px; width: 136px" | Nvidia
|-
| style="height: 10px; width: 152px" | UC San Diego
| style="height: 10px; width: 136px" | eSilicon
|-
| style="height: 10px; width: 152px" | Intel
| style="height: 10px; width: 136px" | Qualcomm
|-
[/table]
Important Dates:
January 1 On-line registration opens
February 27 Submission Deadline
March 13 Acceptance Notification
March 27 Camera Ready Copy
Apr. 21 On-site check-in
ieee-edps.org - program, registration– watch for updates.
www.jdvhotels.com/hotels/california/monterey-hotels/monterey-tides/
April 21 & 22, 2016
Monterey Tides Hotel, Monterey, CA
Sponsored by:
IEEE Computer Society of Silicon Valley (CS-SCV)
Design Automation Technical Committee (DATC)
Council on Electronic Design Automation (CEDA)
The Electronic Design Processes Symposium (EDPS) provides a forum for a cross-section of the top thinkers, movers, and shakers who focus on how chips and systems are designed, and to discuss state-of-the-art electronic design processes and CAD methodologies. The symposium focuses on the improvement of the overall design process, rather than on the functions of the individual tools themselves.
EDPS Home Page[table] align="right" border="1" style="width: 313px"
|-
| colspan="2" style="height: 26px; width: 313px" | 2016 Keynote Speakers
|-
| style="height: 26px; width: 139px" | Ken Caviasca
| style="height: 26px; width: 174px" | VP, R&D, Intel
|-
| style="height: 26px; width: 139px" | Serge Leef
| style="height: 26px; width: 174px" | GM, Mentor Graphics
|-
| style="height: 26px; width: 139px" | Cmdr. Chris Eagle
| style="height: 26px; width: 174px" | Sr. Lecturer, Naval Post Graduate School
|-
[/table]
Thursday 4/21 Session Themes:
- Prototyping IOT Designs
- Low Power Design Methodology
- Multi-Die IC Design & Applications
Friday 4/22 Security Day & Workshop:
- Cyber Security & Hardware Hacking Workshop
- Side Channel Analysis FIPS 140 L2 Workshop
- Fault Injection FIPS 140 L4 Workshop
Authors should submit full-length, original, and unpublished abstracts, presentations & posters along with author’s contact information. Proposals for special, poster, and panel sessions may also be submitted; a one-page description along with organizer’s contact information is required. Send presentations, and proposals to: edps-committee@googlegroups.com with “2016 proposed paper” in the Subject: line.
[table] align="right" border="1"
|-
| colspan="2" style="height: 10px; width: 288px" | Sample of Companies
Present in 2015:
|-
| style="height: 10px; width: 152px" | Oracle
| style="height: 10px; width: 136px" | Cadence
|-
| style="height: 10px; width: 152px" | Samsung
| style="height: 10px; width: 136px" | Stanford Univ.
|-
| style="height: 10px; width: 152px" | ASE
| style="height: 10px; width: 136px" | Synapse
|-
| style="height: 10px; width: 152px" | Mentor
| style="height: 10px; width: 136px" | Synopsys
|-
| style="height: 10px; width: 152px" | Global Foundries
| style="height: 10px; width: 136px" | Nvidia
|-
| style="height: 10px; width: 152px" | UC San Diego
| style="height: 10px; width: 136px" | eSilicon
|-
| style="height: 10px; width: 152px" | Intel
| style="height: 10px; width: 136px" | Qualcomm
|-
[/table]
Important Dates:
January 1 On-line registration opens
February 27 Submission Deadline
March 13 Acceptance Notification
March 27 Camera Ready Copy
Apr. 21 On-site check-in
ieee-edps.org - program, registration– watch for updates.
www.jdvhotels.com/hotels/california/monterey-hotels/monterey-tides/
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