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Hi, I just wanted to bring your attention (politely!) to a research contest in analog design at Patexia. The contest asks for published material pre-dating a certain patent (prior art) and offers a $5000 prize for the best submission. The patent in question features a charge pump in a voltage controlled oscillator. If you're interested in participating, more details can be found here: http://bit.ly/UHxaAL
We request previously undiscovered prior art (If you're new, see: patent and prior art basics and tips for Patexia's prior art contests) including patents and non-patent literature (English and foreign language) that can help invalidate US patent 5,825,640. The best submission is guaranteed to receive the prize.
This study of US patent 5,825,640 relates to a charge pump circuit used in a Phase Locked Loop (PLL) block as part of a RF receiver system.
One of the key features of this design is the presence of a charge conduction path (transistors 42 and 43 in the following circuit diagram) to discharge the parasitic capacitance of nodes 38 and 39 into the discharge node of 45 and as a result reduce the error current in the output. The charge conduction path is enabled only on one transition edge of the input pulse and is disabled on the other transition edge of the input pulse to isolate the node from the output.
Requirements:
Submission Notes
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We request previously undiscovered prior art (If you're new, see: patent and prior art basics and tips for Patexia's prior art contests) including patents and non-patent literature (English and foreign language) that can help invalidate US patent 5,825,640. The best submission is guaranteed to receive the prize.
This study of US patent 5,825,640 relates to a charge pump circuit used in a Phase Locked Loop (PLL) block as part of a RF receiver system.
One of the key features of this design is the presence of a charge conduction path (transistors 42 and 43 in the following circuit diagram) to discharge the parasitic capacitance of nodes 38 and 39 into the discharge node of 45 and as a result reduce the error current in the output. The charge conduction path is enabled only on one transition edge of the input pulse and is disabled on the other transition edge of the input pulse to isolate the node from the output.
Requirements:
- Reference published before June 30th 1997
- Charge pump circuit that recognizes the presence of a parasitic capacitor, and teaches discharging of the parasitic capacitor after each cycle
- Charge pump circuit that is part of a PLL inside a wireless receiver
- A charge pump circuit similar to the above circuit diagram. In particular we are interested to see transistors 42, 43 and the unity gain amplifier of 44.
- A charge pump circuit similar to the following circuit diagram. In particular we are interested to see transistors 40, 41 in the charge pump design.
- A charge pump circuit similar to the following circuit diagram? In particular we are interested to see transistors 36 and 37.
Submission Notes
- Submission deadline is October 14, 2012
- All work must be prepared by a single researcher
- Maximum of one entry per person allowed
- Entries must be in English
- References can be in any language
- If your reference has already been submitted or is not acceptable, the system will automatically reject it
- In case you are submitting foreign references, please provide a translation of key sections
- You are only permitted to submit one entry and you will not be able to edit it after submitting
- All submissions are subject to Patexia's contest legal terms. Failure to follow these rules may lead to disqualification from the contest
- For questions, email contests@patexia.com
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