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AMD takes over MEXT for memory tiering tech that enables 3D NAND flash to appear as DRAM to the OS in AI applications

F

Fred Chen

Moderator

AMD takes over MEXT for memory tiering tech that enables flash to appear as DRAM to applications — tech to 'address growing memory constraints' in the data center​

By Anton Shilov published June 16, 2026
AMD gains a team of experienced engineers too.

AMD on Monday announced that it had acquired MEXT, a startup that developed a memory tiering technology that makes NAND flash memory appear as DRAM to the operating system, which enables operators of data centers to save money on DRAM. AMD expects the acquisition to help customers improve system efficiency, lower operating costs, and deploy large-scale workloads more quickly.

As AI models continue to expand and datasets grow larger, memory availability has become an increasingly important factor affecting overall system performance. In many cases, memory resources, not CPUs or GPUs, are becoming a performance bottleneck. Meanwhile, in many cases DRAM is used inefficiently.

MEXT addresses memory efficiency challenges with an AI-based memory tiering technology that moves infrequently accessed data from expensive DRAM to NAND storage, which costs orders of magnitude less per unit of capacity, and in a way that's transparent to applications. MEXT's Predictive Memory Engine continuously analyzes memory access patterns and uses AI models to anticipate which data stored in flash will be needed next. Those memory pages are proactively transferred back into DRAM before applications request them and enable software to access data as though it were in main memory, thus preserving performance levels.

By increasing the amount of usable memory available to applications, MEXT's technology aims to improve utilization of existing infrastructure and at the same time reduce needs for expensive DRAM. This approach can potentially lower total cost of ownership for cloud providers and enterprise customers and enable larger workloads to run on existing hardware. AMD believes that these capabilities can benefit both traditional data center applications and modern AI deployments, where access to large memory pools is often critical for efficiency and scalability.

AMD plans to incorporate MEXT's technology into its data center product portfolio and expand its capabilities to address memory-hungry AI workloads. The company already offers integrated solutions that combine processors, accelerators, networking technologies, and software, so MEXT's Predictive Memory Engine will complement the already broad portfolio.

 
Sølve Folkestad Dahl said:
Shouldn't the OS be doing this?
Click to expand...
You could, but it would be too slow without chip-level hardware acceleration. You need specialized hardware acceleration to make memory tiering fast enough to be a benefit. (CPUs do this for OS page tables.)

Companies in the CXL consortium are "experimenting" with memory tiering. CXL calls it "active memory tiering". CXL is also experimenting with near-memory compute, a concept that gets people excited, but the products haven't succeeded in widespread implementation yet. So far, I haven't seen much of industry implementation and deployment with CXL (has anyone?), and what CXL discusses is much simpler in implementation than what MEXT describes.

The cycle time differences between DRAM and NAND flash look very challenging for the MEXT concept as described. The video on their website speaks of using AI concepts to identify memory segments for migration to and from NAND, but the discussion is more marketing than substance. Until AMD/MEXT can produce before and after test results to show the performance and DRAM saving benefits, I'd be very skeptical about betting on this technology. I'm also wondering how MEXT deals with the limited endurance of NAND flash for writes as systems age.

AMD's track record with these aspirational acquisitions isn't very good either, which isn't confidence inspiring. And MEXT technology looks very complicated to engineer into silicon.
 
Last edited:
blueone said:
I'm also wondering how MEXT deals with the limited endurance of NAND flash for writes as systems age.
Click to expand...
The endurance is an important consideration. Presumably, they will use overprovisioning, although that will only go so far, because it is, of course, going to be expensive.

If they target 1e8 cycles, and the expected endurance is 1e5 cycles, for example, you might expect capacity on the order of TB to cover on the order of GB.
 
Fred Chen said:
The endurance is an important consideration. Presumably, they will use overprovisioning, although that will only go so far, because it is, of course, going to be expensive.

If they target 1e8 cycles, and the expected endurance is 1e5 cycles, for example, you might expect capacity on the order of TB to cover on the order of GB.
Click to expand...
Your calculation made me chuckle. You showed the calculated cost for over-provisioning makes it unacceptable. I just suspected it. :)

I see a few possibilities they might have factored in:

1. MEXT thinks writes to NAND are relatively rare compared to reads in their design for their target applications.

2. MEXT is using a DRAM read cache to group NAND writes and reduce thrashing back and forth when the applications do not follow their design assumptions strictly. Intel did this with a DRAM cache in the CPU (or chipset, I don't remember which anymore) to increase effective Optane DIMM write endurance.

3. MEXT could be using SLC NAND, which has 10x or more the write endurance of MLC NAND. That doesn't eliminate write endurance as a factor, but in combination with the other two possibilities might make NAND practical in this application.
 
blueone said:
Your calculation made me chuckle. You showed the calculated cost for over-provisioning makes it unacceptable. I just suspected it. :)

I see a few possibilities they might have factored in:

1. MEXT thinks writes to NAND are relatively rare compared to reads in their design for their target applications.

2. MEXT is using a DRAM read cache to group NAND writes and reduce thrashing back and forth when the applications do not follow their design assumptions strictly. Intel did this with a DRAM cache in the CPU (or chipset, I don't remember which anymore) to increase effective Optane DIMM write endurance.

3. MEXT could be using SLC NAND, which has 10x or more the write endurance of MLC NAND. That doesn't eliminate write endurance as a factor, but in combination with the other two possibilities might make NAND practical in this application.
Click to expand...
Yes, the SLC would be the only way to maximize the endurance. I'm not sure how realistic the rarity of writing to NAND would be to justify the cost.
 
bilau said:
SLC isn't cheap. And bigger Nand vendors have either discontinued it or issued last time buy.
Click to expand...
3D NAND is usually sold as TLC, but they can be operated in "pseudo-SLC" mode. It would be the only feasible way to raise endurance. There have been some SLC SSDs with 3D NAND with the much better endurance, such as Gigabyte.
 
Fred Chen said:

AMD takes over MEXT for memory tiering tech that enables flash to appear as DRAM to applications — tech to 'address growing memory constraints' in the data center​

By Anton Shilov published June 16, 2026
AMD gains a team of experienced engineers too.

AMD on Monday announced that it had acquired MEXT, a startup that developed a memory tiering technology that makes NAND flash memory appear as DRAM to the operating system, which enables operators of data centers to save money on DRAM. AMD expects the acquisition to help customers improve system efficiency, lower operating costs, and deploy large-scale workloads more quickly.

As AI models continue to expand and datasets grow larger, memory availability has become an increasingly important factor affecting overall system performance. In many cases, memory resources, not CPUs or GPUs, are becoming a performance bottleneck. Meanwhile, in many cases DRAM is used inefficiently.

MEXT addresses memory efficiency challenges with an AI-based memory tiering technology that moves infrequently accessed data from expensive DRAM to NAND storage, which costs orders of magnitude less per unit of capacity, and in a way that's transparent to applications. MEXT's Predictive Memory Engine continuously analyzes memory access patterns and uses AI models to anticipate which data stored in flash will be needed next. Those memory pages are proactively transferred back into DRAM before applications request them and enable software to access data as though it were in main memory, thus preserving performance levels.

By increasing the amount of usable memory available to applications, MEXT's technology aims to improve utilization of existing infrastructure and at the same time reduce needs for expensive DRAM. This approach can potentially lower total cost of ownership for cloud providers and enterprise customers and enable larger workloads to run on existing hardware. AMD believes that these capabilities can benefit both traditional data center applications and modern AI deployments, where access to large memory pools is often critical for efficiency and scalability.

AMD plans to incorporate MEXT's technology into its data center product portfolio and expand its capabilities to address memory-hungry AI workloads. The company already offers integrated solutions that combine processors, accelerators, networking technologies, and software, so MEXT's Predictive Memory Engine will complement the already broad portfolio.

Click to expand...

Isn't it similar to the Phison's aiDAPTIV / aiDAPTIV+?
 
bilau said:
SLC isn't cheap. And bigger Nand vendors have either discontinued it or issued last time buy.\

They may be harder to get than DRAM.
Click to expand...
I might be out of date. Samsung used so-called "Z-NAND" to compete with Optane SSDs. Solidigm and Kioxia had similar SLC (or SLC-like) products, which I believe are still sold. So I thought SLC was still available in one form or another. And even SLC is still a lot cheaper than DRAM.
 
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