You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please, join our community today!
Douglas C. Youvan
doug@youvan.com
www.youvan.ai
January 16, 2026
The question of whether Taiwan Semiconductor Manufacturing Company (TSMC) would be destroyed in a Chinese invasion of Taiwan is often framed as speculative, controversial, or hypothetical. In reality, the accumulated logic of...
Interesting comment from CFO here at Morgan Stanley conference back in March: https://ca.investing.com/news/transcripts/intel-at-morgan-stanley-conference-strategic-shifts-and-challenges-93CH-4495199
"As you might imagine, you know, when you’re, when you’re trying to like lock yields down and...
Technology analyst Jukan pointed out on social media that, according to a report issued by Morgan Stanley, Intel's 18A process (compared to TSMC's 2nm) has a yield rate of only 50%, and the company is currently working hard to improve its yield level. The report indicates that customers have a...
Also brought up that's very interesting:
1. Intel 18A nanosheet vertical uniformity is better than SF2.
2. Samsung added a Heat Path Block (HPB), basically a heat sink above the CPU/GPU, sitting right next to the DRAM.
The metric 2/(CPP*Cell height) itself is not an issue since that information can be pulled for all the competitors; in fact, it might offer more clarity independent from layout utilization. The issue here is the formula should explicitly and unambiguously mention the use of stacking vertical...
I see now, they plotted 2/(CPP*Cell Height). So this corresponds to ~114 MTr/mm2 if using the D_design formula, as expected for N+3. So then, to get to 238 from 155, LogicFolding is effectively reducing cell height and/or gate pitch?
Arguably, making M2 the same pitch as M0 even by SAQP would...
Currently there is a report or rumor that Samsung is testing its 1.4nm on the next Exynos: https://wccftech.com/next-generation-exynos-tested-on-1-4nm-process-reveals-96mb-slc-cache-and-more/ but this soon suggests more likely not High-NA.
I don't know if there has been a generally or widely accepted formula. I use 1.474/(CPP*cell height), it would be near the upper end of the D_design shown above. It comes from 60% NAND2 (3 CPP wide), 40% Flip flop (19 CPP wide).
They have the ability to catch up, they just have to port their M2 to the same pitch as their M0. But with the speaker's emphasis on time instead of geometry scaling, it suggested they want to change the game.
Just saw this: https://www.huaweicentral.com/huawei-kirin-2026-chip/
Huawei has revealed its Kirin 2026 details and it reveals massive upgrade in the chip architecture including transistor density.
He Tingbo, Director and President of Semiconductor Business, revealed the Tao (τ) Law for chip...
In a major bid to bypass crippling U.S. technology sanctions, China’s Huawei Technologies has unveiled an ambitious semiconductor roadmap, projecting the design of high-end chips with a transistor density equivalent to a 1.4-nanometer (1.4-nm) process node by 2031.
The announcement was made on...
May 23, 2026 - 9:37 am Story byAna Maria Constantin
Corsair DDR5 modules spotted with Chinese CXMT chips as AI demand starves PCs of DRAM. Prices may fall in H2 2027
Corsair, one of the most recognisable names in PC components, is shipping DDR5 memory modules built with DRAM manufactured by...
