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The endurance is an important consideration. Presumably, they will use overprovisioning, although that will only go so far, because it is, of course, going to be expensive.
If they target 1e8 cycles, and the expected endurance is 1e5 cycles, for example, you might expect capacity on the order...
AMD takes over MEXT for memory tiering tech that enables flash to appear as DRAM to applications — tech to 'address growing memory constraints' in the data center
By Anton Shilov published June 16, 2026
AMD gains a team of experienced engineers too.
AMD on Monday announced that it had acquired...
It's possible different individuals in China could have specialized knowledge about specific components of an ASML EUV system, e.g., mirror, source, etc. But it still takes an integrator with the accumulated decades of experience among many people like ASML to put it all successfully together...
From looking at these patents, it looks like the response from TSMC would be that they aren't being practiced or that they are so obvious from even earlier prior art that these patents should have been invalidated. Note that these patents originated with UMC. UMC most likely considered these...
Here is Gemini's list of the relevant 5 patents:
1. Raised Epitaxial Transistor Structures
The Patent: U.S. Patent No. 7,745,847 ("Metal Oxide Semiconductor Transistor"). [1]
What it covers: This patent covers a specific method for structuring the source and drain regions of a transistor using...
US claims China has ASML tool
RESTRICTION BREACH: ASML said that it denies ‘unfounded rumors regarding non-compliance with export controls concerning China,’ and enforces controls strictly
US Secretary of Commerce Howard Lutnick in a series of recent meetings outlined concerns to Dutch...
TSMC suit may be patent trolls
BAD FAITH LITIGATION? The two companies, owned by a California-based private equity firm, could be seeking licensing fees or a settlement payout with the suit
Taiwan Intellectual Property Office (TIPO) Director-General Liao Cheng-wei (廖承威) said yesterday he...
One other important consideration for high NA is stitching. I don't think Intel can skirt around it. The High-NA scanner's throughput will depend on die/chiplet height even when stitching is not needed between parts of the chip. It's because of different numbers of row scans (2-3 shown below) to...
It was a measure of confidence against "variability risk", the "variability" not being stochastics, but process steps, e.g., overlay, feature tone reversal, etc..
So I went through the whole presentation just now. I am not sure why only one slide was posted originally by someone to make some judgments about High-NA vs. SALELE. This slide was actually in the middle of the talk, where the processes were compared to highlight that High-NA direct print would...
28 nm pitch was hinted at in an SPIE paper last year.
There's no advantage for increasing NA from 0.33 to 0.55 for a 28 nm pitch. The image formation is the same (2-beam).
The larger beam's angle for 0.33 NA has a lower mask multilayer reflectivity vs. 0.55 NA, which would lead to a ~10% dose...
