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Search results

  1. F

    Memory will not be an issue in 5 years.

    CXMT said to be going to 1a or 1b later this year: 1b would be a particularly difficult transition.
  2. F

    Memory will not be an issue in 5 years.

    1d (arriving 2027) is largely seen as the last conventional (6F2) DRAM node. Then, different players have different paths. Some will go 4F2, some will skip, going directly to 3D.
  3. F

    SMIC Begins Testing Domestic Immersion DUV Lithography Tool

    This is a good reminder to maintain realistic expectations of China's progress. We should also be reminded that many immersion-related patents from ASML and Nikon have expired or are expiring soon, so they will be in time to make use of the same technologies.
  4. F

    SMIC Begins Testing Domestic Immersion DUV Lithography Tool

    The Financial Times report was from September. That article cannot be accessed freely now. Other reports based on that article are still available, such as: https://finance.yahoo.com/news/chinas-largest-chipmaker-testing-first-141115657.html It is said to resemble ASML's Twinscan NXT:1950i...
  5. F

    SMIC Begins Testing Domestic Immersion DUV Lithography Tool

    Author: AXTEK Technology Company Limited China’s leading foundry, SMIC (Semiconductor Manufacturing International Corp.), has begun testing a domestically manufactured immersion DUV lithography machine. According to the Financial Times, the tool was developed by Yuliangsheng, a Shanghai-based...
  6. F

    More than Moore - IBM Announces 0.7nm Process Node (Significant logic/SRAM scaling vs 2nm)

    It's strikingly similar to Huawei's Logic Folding, my feeling.
  7. F

    DRAM/HBM supply-demand balance

    So that seems to be the core of the problem (or their intent). They are stepping off the gas for regular consumer DRAM, in order to focus on the HBM.
  8. F

    CXMT targeting over 500Mb/mm2 with 64-layer 3D DRAM test vehicle

    Abstract: Stacked dynamic random access memory (DRAM) technology has garnered considerable attention as a means to continue the relentless pursuit of scaling. In this context, we have developed a five-layer horizontal cell with vertical word line (WL) and pillar capacitor to realize a stacked...
  9. F

    DRAM/HBM supply-demand balance

    https://www.trendforce.com/news/2026/06/26/news-micron-reportedly-acknowledges-chinas-memory-progress-while-noting-output-remains-largely-domestic/ Amid market chatter that big tech firms are reportedly evaluating Chinese memory products, Micron, during its earnings call, acknowledged the...
  10. F

    DRAM/HBM supply-demand balance

    Oh it's hardly a piece of cake. Transistor structure is all different. High aspect ratio capacitor. You can only get good margins from reuse of modules. Reviving 3D XPoint might be easier and better timing.
  11. F

    DRAM/HBM supply-demand balance

    DRAM would require substantially new process development and it is also an expensive process. In their recent collaboration with SAIMEMORY, they didn't provide the DRAM but the packaging technology.
  12. F

    U.S.-backed chip startup xLight aims to raise $350 million for an EUV alternative

    What would be the extent of ASML's mentioned collaboration with xLight, I wonder.
  13. F

    DRAM/HBM supply-demand balance

    The report's sampling is weird. It has JHICC but not Winbond? Is macrostream.ai an AI site?
  14. F

    DRAM/HBM supply-demand balance

    SK hynix was most aggressive or active in promoting 4F2 at the VLSI conference this year. It looks like they're stopping the 6F2 architecture at 1d. The EUV is apparently a big burden, and they say 4F2 relieves this, besides providing electrical benefits. I find it hard to imagine more than 3...
  15. F

    US Commerce Secretary Lutnick claims China has ASML EUV tool

    In many papers, they paired the EUV print (from their synchrotron) with an EBL print, which usually looked better.
  16. F

    AMD takes over MEXT for memory tiering tech that enables 3D NAND flash to appear as DRAM to the OS in AI applications

    Yes, very similar, using SSD offload. AMD seems to be targeting the data center mainly.
  17. F

    U.S.-backed chip startup xLight aims to raise $350 million for an EUV alternative

    Higher EUV power is definitely not pellicle-compatible, and likely will become resist-incompatible as well.
  18. F

    Chinese RAM Kits Adopt Homegrown 24 Gb DDR5 Memory Modules

    Chinese companies like Gloway and KingBank, which provide DDR5 memory kits for consumer platforms, have started integrating domestically produced CXMT DDR5 memory into their RAM kits, effectively ending their reliance on DRAM from Micron, SK hynix, and Samsung after years of external dependence...
  19. F

    AMD takes over MEXT for memory tiering tech that enables 3D NAND flash to appear as DRAM to the OS in AI applications

    3D NAND is usually sold as TLC, but they can be operated in "pseudo-SLC" mode. It would be the only feasible way to raise endurance. There have been some SLC SSDs with 3D NAND with the much better endurance, such as Gigabyte.
  20. F

    AMD takes over MEXT for memory tiering tech that enables 3D NAND flash to appear as DRAM to the OS in AI applications

    Yes, the SLC would be the only way to maximize the endurance. I'm not sure how realistic the rarity of writing to NAND would be to justify the cost.
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