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The red line trend is actually the plot of Density = 2 transistors/(gate pitch * cell height).
They do state the 60-75% utilization factor, following the density formula. They are likely using 7nm node pitches, but can't rule out a reduction in cell height (i.e., less tracks). Die area...
He did not specify in the clip why China will come out winning in the end (more power than anyone else, probably have more chips), maybe there were was something mentioned earlier.
If Huawei defined the transistor density as 2/(gate pitch * cell height), and it's going from 155 to 238 MTr/mm2, it suggests that there is a big reduction in cell height. 155 MTr/mm2 is consistent with 57 nm gate pitch and six tracks of 38 nm pitch (228 nm cell height), while 238 MTr/mm2 is...
I think a fair comparison would have the 3DXPoint dies linked by TSVs just like HBF and HBM (for 3D NAND and DRAM dies, respectively). The cost and performance were already not good enough for the 3D XPoint by itself to support a large enough market.
The DRAM and NAND prices have gone up, but I...
Intel Fab 52 construction alone cost over 5 billion: https://www.enr.com/articles/62647-offsite-assembly-high-velocity-design-help-deliver-arizona-intel-fab-plant
AI demand, particularly HBM demand, has gone up more than fab capacity can handle. Normally, higher prices would reduce demand from consumers, which in turn, would lead prices down. But consumers' demand no longer seems to matter compared to the hyperscalers, who are willing to pay more. Since...
CFO Zinsner insists the troubled node was a one-off as 14A stays on track
Published Wed 03 Jun 2026 // 16:20 UTC
Intel is keen to reassure investors that its troubles with the 18A manufacturing process were a one-off, and that it is better positioned to capitalize on what it expects will be...
This teardown by Kurnal was posted on X yesterday: https://x.com/i/status/2062125652288131276
Pitches are listed there, but the really interesting finding to me was that the number of M2P tracks in the cell height went from 6 to 5. Still 6 M0 pitches within the cell height though. No buried rails.
Douglas C. Youvan
doug@youvan.com
www.youvan.ai
January 16, 2026
The question of whether Taiwan Semiconductor Manufacturing Company (TSMC) would be destroyed in a Chinese invasion of Taiwan is often framed as speculative, controversial, or hypothetical. In reality, the accumulated logic of...
Interesting comment from CFO here at Morgan Stanley conference back in March: https://ca.investing.com/news/transcripts/intel-at-morgan-stanley-conference-strategic-shifts-and-challenges-93CH-4495199
"As you might imagine, you know, when you’re, when you’re trying to like lock yields down and...
Technology analyst Jukan pointed out on social media that, according to a report issued by Morgan Stanley, Intel's 18A process (compared to TSMC's 2nm) has a yield rate of only 50%, and the company is currently working hard to improve its yield level. The report indicates that customers have a...
