Array
(
    [content] => 
    [params] => Array
        (
            [0] => /forum/search/542382/?c%5Busers%5D=Fred+Chen&o=date&page=4
        )

    [addOns] => Array
        (
            [DL6/MLTP] => 13
            [Hampel/TimeZoneDebug] => 1000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000970
            [ThemeHouse/XPress] => 1010570
            [XF] => 2031070
            [XFI] => 1060170
        )

    [wordpress] => /var/www/html
)

Search results

  1. F

    Nanya Technology becomes LPPDR5 supplier for NVIDIA

    Servers using NVIDIA's Vera Rubin CPU use LPPDR5X DRAM, and Nanya Technology has been reported to have become a supplier. Yet its technology stage is 2nd-generation 10nm-class, same level as CXMT's G3 process already available in 2024. It is also hinted that TSMC assisted with the stacking...
  2. F

    NEO Semiconductor's 3D X-DRAM for AI processors has passed proof-of-concept validation — company secures funding to develop next-gen HBM alternative

    These days, a new DRAM technology like IGZO, they often test to 1e11-1e12 cycles. Really we expect should go to 1e15 cycles, but that's 3 years of 100 ns cycles.
  3. F

    NEO Semiconductor's 3D X-DRAM for AI processors has passed proof-of-concept validation — company secures funding to develop next-gen HBM alternative

    From: https://www.thelec.net/news/articleView.html?idxno=6808 "The 10a node represents the first generation below 10 nanometers, with actual line widths estimated at around 9.5 to 9.7 nanometers." "The company plans to use the 4F² and VCT structures across three generations — 10a, 10b and 10c...
  4. F

    NEO Semiconductor's 3D X-DRAM for AI processors has passed proof-of-concept validation — company secures funding to develop next-gen HBM alternative

    By Etiido Uko published 17 hours ago Next-gen memory designed as a lower-cost, lower-power HBM alternative for AI workloads NEO Semiconductor 3D X-DRAM (Image credit: NEO Semiconductor) NEO Semiconductor announced on April 23rd that its 3D X-DRAM technology has successfully passed...
  5. F

    Exclusive: Intel Tells Staff It Will Disclose Scope Of Work With Elon Musk In ‘Coming Weeks’

    Intel licensing 14A process to Terafab is like weaning them off, if not creating a competitor.
  6. F

    Tesla Earnings Call - Intel 14A, Research (Tera)Fab details, Supplier Leverage?

    Indeed, with the targeted output of Terafab being so much larger, they'd become the foundry rival to Intel.
  7. F

    Tesla Earnings Call - Intel 14A, Research (Tera)Fab details, Supplier Leverage?

    So they wish to transfer the 14A process from Intel to Terafab?
  8. F

    Exclusive: Intel Tells Staff It Will Disclose Scope Of Work With Elon Musk In ‘Coming Weeks’

    By Dylan Martin April 14, 2026, 5:30 PM EDT ‘[Elon Musk’s] expansive vision across AI, transportation, communications, robotics and space travel relies heavily on an ample and uninterrupted supply of silicon chips. Intel is thus a natural partner to help him realize his vision,’ Intel CEO...
  9. F

    ASML lifts 2026 forecast as surging AI chip demand boosts new orders

    Going by this latest reference: https://www.semi.org/sites/semi.org/files/2023-11/07%20Carlo%20Luijten%20NNNN.pdf The throughput is reduced 27.5% by going from 30 to 60 mJ/cm2, so from 220 WPH to 160 WPH, for example.
  10. F

    ASML lifts 2026 forecast as surging AI chip demand boosts new orders

    He's still quoting throughput at 30 mJ/cm2, should be at 60 mJ/cm2. I wonder how bad it is at that dose.
  11. F

    ASML lifts 2026 forecast as surging AI chip demand boosts new orders

    Sharp drop in ArFi revenue, could that be China?
  12. F

    Samsung GAA SF2, Exynos 2600, cross-section images

    It looks like their "M0" shows 6 tracks (4 signal lines + 2 rails): So if it's 168 nm cell height, the M0 is actually 28 nm pitch.
  13. F

    Inside Nanya Technology’s Turnaround: Why Global Memory Giants Are Buying In

    Nanya licensed 1x and 1y from Micron: https://investors.micron.com/news-releases/news-release-details/micron-technology-license-1x-and-1y-dram-technologies-nanya Disappointingly, Nanya decided to play a node naming game, calling its latest node "1B" when it is actually closer to CXMT G3 (~1x)...
  14. F

    Logic Contact from W to Mo, a press release by Applied Materials

    Isn't the key motivation that Mo doesn't need a barrier liner, so it could fill more of the smaller contact?
  15. F

    Intel CEO embraces its 18A node for external customers as 18A-P gets 'inbound interest' — company cites increasing yields

    It shouldn't make much difference, the pitch determines the resist thickness, which determines how many photons absorbed. This is the latest study of 36 L/S nm pitch by Samsung: https://www.nature.com/articles/s41598-025-29021-2
  16. F

    Samsung and SK are expanding fast, but why is memory still in short supply?

    I had gathered from TechInsights that the array area efficiency was just over 50% for 1b (LP)/DDR5, but also from them I only have one data point for HBM3 (1z), the array area efficiency was just under 50%.
  17. F

    Intel CEO embraces its 18A node for external customers as 18A-P gets 'inbound interest' — company cites increasing yields

    The baseline defectivity is high even for a 40 nm pitch: Since it fluctuates, you can have very good yield at times, very bad also. Stochastics hasn't been truly solved, accepted perhaps.
  18. F

    Samsung and SK are expanding fast, but why is memory still in short supply?

    Not many HBM teardowns available but I had taken recent die area efficiency for the array ~50%, with TSVs ~10% (a strip down the middle). I might be over-generalizing though.
  19. F

    Samsung and SK are expanding fast, but why is memory still in short supply?

    Yes, the HBM TSVs have a keep-out-zone which will still take up a "small" % of the area.
Back
Top