Samsung GAA SF2, Exynos 2600, cross-section images

[NY_Sam2]

Samsung GAA SF2, Exynos 2600, cross-section images
. M0 signal lines between Vdd & GND = 5 for SF4/SF3E to 4 for SF3/SF2
. SF2 Cell Height = ~170nm? no scale bar in the images!
. source = https://chipwise.tech/our-portfolio/gate-all-around-analysis/

 

[Fred Chen]

2nm track pitch ~ 23 nm, going by this: https://gamma0burst.tistory.com/413218#google_vignette

 

[LLL0955]

WTF.

SF2 dimension is the same as SF3…

So Samsung density no improve through 2023 SF3 break cover….

https://twitter.com/x/status/2041853845148725543

 

[NY_Sam2]

. Samsung SF2 M0 26nm! in 2025
. Samsung SF2P M0 24nm? in 2026
. still larger than TSMC N3/N3E M0 23nm since 2022-Dec-IEDM

 

[Fred Chen]

. Samsung SF2 M0 26nm! in 2025
. Samsung SF2P M0 24nm? in 2026
. still larger than TSMC N3/N3E M0 23nm since 2022-Dec-IEDM

View attachment 4426

WTF.

SF2 dimension is the same as SF3…

So Samsung density no improve through 2023 SF3 break cover….

https://twitter.com/x/status/2041853845148725543

It looks like their "M0" shows 6 tracks (4 signal lines + 2 rails):

So if it's 168 nm cell height, the M0 is actually 28 nm pitch.

 

[LLL0955]

Power rail is larger than signal track, and M0 pitch is more refer to signal track pitch

 

[Fred Chen]

Power rail is larger than signal track, and M0 pitch is more refer to signal track pitch

Yes.

 

[LLL0955]

Final

https://twitter.com/x/status/2045421893365440861

 

[Fred Chen]

So like CGP, we're seeing M2P leveling off around 28 nm?

 

[Fred Chen]

This teardown by Kurnal was posted on X yesterday: https://x.com/i/status/2062125652288131276

Pitches are listed there, but the really interesting finding to me was that the number of M2P tracks in the cell height went from 6 to 5. Still 6 M0 pitches within the cell height though. No buried rails.