March 13, 2013July 18, 2025

Ensuring timing of Custom Designs with large embedded memories – A big burden has solution!

Ensuring timing of Custom Designs with large embedded memories – A big burden has solution!
by Pawan Fangaria on 03-13-2013 at 10:30 am
Categories: EDA, Synopsys

In 1990s when designs were small, I was seeing design and EDA community struggling to improve upon huge time taken to verify the circuits, specifically with Spice and the like. I was myself working on developing tool for transistor level static timing analysis (STA) mainly to gain on time (eliminating the need of exhaustive set … Read More

November 11, 2012July 18, 2025

Static Timing Analysis for Memory Characterization

Static Timing Analysis for Memory Characterization
by Daniel Payne on 11-11-2012 at 6:18 pm
Categories: EDA, Synopsys

Modern SoC (System On Chip) designs contain a larger number of RAM (Random Access Memory) instances, so how do you know what the speed, timing and power are for any instance? There are a couple of approaches:
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Trust the IP supplier to give you models that use polynomial equations to curve-fit the performance numbers based