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SmartDV Wiki

Published by Admin on 04-20-2020 at 2:40 pm
Last updated on 07-14-2020 at 1:25 pm

SmartDV — The Smart Choice for Design and Verification IP

SmartDV is the Proven and Trusted choice for Verification and Design IP with the best customer service from more than 250 experienced ASIC and SoC design and verification engineers.

Our high-quality standard or custom protocol Verification and Design IP is compatible with all verification languages, platforms and methodologies supporting all simulation, emulation and formal verification tools used in a coverage-driven chip design verification flow.

The result is Proven and Trusted Verification and Design IP used in hundreds of networking, storage, automotive, bus, MIPI and display chip projects throughout the global electronics industry.

About SmartDV

SmartDV™ Technologies is the Proven and Trusted choice for Smart Verification Solutions™ that range from Verification IP, including assertion-based and post-silicon validation IP, to synthesizable transactors, memory models and Design IP. Used in hundreds of design projects throughout the global electronics industry, engineering groups rely on SmartDV’s Verification IP solutions developed by talented and experienced ASIC and SoC design and verification engineers.

SmartDV’s Strengths:

— Proven Track Record with a large, repeat user base who Trust SmartDV’s Verification IP solutions

— Largest, most extensive up-to-date Verification IP portfolio for a variety of chip design verification projects firmly positioning SmartDV as the Proven and Trusted provider of Smart Verification Solutions™

— Proven and Trusted expertise that spans the chip design and verification experience space

— SmartDV’s Proven and Trusted proprietary automated compiler-based technology enables rapid development and deployment of new Verification IP to support new industry standard protocols and on-demand customization

Products

  • Verification IP’s

We develop Verification Components, leveraging our rich experience in ASIC / SoC design verification and capabilities on high-level verification languages (HVLs). Our verification components are configurable, reusable plug-and-play verification solutions for standard interfaces based on HVL. We currently support SystemVerilog, Vera, SystemC, Specman E and Verilog. All our VIP’s are supported natively in SystemVerilog VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env.

All our verification components comes with advanced commands, configurations and status reporting interface. This is very simple to use and debug. We use lot of automation for writing Verification IP, so time to develop any verification IP is very efficient and faster. If you need any verification IP which is not listed below, please do let us know. We can develop it very fast for you.

We have more than 100 customers using our Verification IP’s. Most of the top semiconductor companies are our customers.

List of Verification IPs

  • Memory Model’s

We develop Memory Models, leveraging our rich experience in ASIC / SoC design verification and capabilities on high-level verification languages (HVLs). Our Memory Models are configurable, reusable plug-and-play verification solutions for standard interfaces based on HVL. We currently support SystemVerilog, Vera, SystemC, Specman E and Verilog. All our Memory Models are supported natively in SystemVerilog VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env.

All our Memory Models comes with advanced commands, configurations and status reporting interface. This is very simple to use and debug. We use lot of automation for writing Memory Models, so time to develop any Memory Model is very efficient and faster. If you need any Memory Model which is not listed below, please do let us know. We can develop it very fast for you.

List of Memory Models

  • SimXL – Emulation Models

We develop Synthesizable Transactors(Emulator Models), leveraging our rich experience in ASIC / SoC design verification and capabilities on high-level verification languages (HVLs) and Emulators, Which can run in Veloce/Palladium/Zebu and any custom FPGA platform. Our Synthesizable Transactors(Emulator Models) are configurable, reusable plug-and-play verification solutions for standard interfaces based on HVL. We currently support Verilog for Synthesizable Transactors with UVM/OVM/SystemVerilog/SystemC/C interface for controlling Synthesizable Transactors(Emulator Models). All Synthesizable Transactors(Emulator Models) have been developed to have same functionality as our VIP’s with good performance

All our Synthesizable Transactors(Emulator Models) comes with advanced commands, configurations and status reporting interface. This is very simple to use and debug. We use lot of automation for writing Synthesizable Transactors(Emulator Models), so time to develop any Synthesizable Transactors(Emulator Models) is very efficient and faster. If you need any Synthesizable Transactors(Emulator Models) which is not listed below, please do let us know. We can develop it very fast for you.

We have many top semiconductors who are using our Synthesizable Transactors(Emulator Models).

List of Synthesizable Transactors

  • Formal Verification IP (Assertion IP)

We develop Formal Verification IP (Assertion IP), leveraging our rich experience in ASIC / SoC design verification and capabilities on high-level verification languages (HVLs) and Formal Verification. Our Formal Verification IP(Assertion IP) are configurable, reusable plug-and-play verification solutions for standard interfaces. We currently support SystemVerilog for Formal Verification IP (Assertion IP).

All our Formal Verification IP (Assertion IP) comes with advanced configurations and coverage reporting interface. This is very simple to use and debug. We use lot of automation for writing Formal Verification IP (Assertion IP), so time to develop any Formal Verification IP (Assertion IP) is very efficient and faster. If you need any Formal Verification IP (Assertion IP) which is not listed below, please do let us know. We can develop it very fast for you.

We have many top semiconductors who are using our Formal Verification IP (Assertion IP).

List of Formal Verification IPs

  • Post Silicon Validation IP’s

We develop Post Silicon Validation IP (PSVIP), leveraging our rich experience in ASIC / SoC design and capabilities on Verilog and VHDL, and doing complex SOC Silicon Validation. Our PSVIP are configurable and, reusable plug-and-play PSVIP solutions for standard interfaces. All our SPVIP comes with advanced configuration, Error injection and status reporting interface. All our Post Silicon Validation IP (PSVIP) are validated using our Verification IP’s which has been used to tapeout multiple ASIC by our customers. Also each of Post Silicon Validation IP (PSVIP) is tested on FPGA platform. We use lot of automation for writing Post Silicon Validation IP (PSVIP), so time to develop any Post Silicon Validation IP (PSVIP) is very efficient and faster. If you need any Post Silicon Validation IP (PSVIP) which is not listed below, please do let us know. We can develop it very fast for you.

Note : Our Post Silicon Validation IP (PSVIP) has been used by many top semiconductor companies

List of Post Silicon Validation IPs

  • Design IP’s

We develop Design Components, leveraging our rich experience in ASIC / SoC design and capabilities on Verilog and VHDL. Our Design components are configurable and, reusable plug-and-play design solutions for standard interfaces based on Verilog and VHDL. All our design components comes with advanced configuration and status reporting interface. All our Design components are validated using our Verification IP’s which has been used to tapeout multiple ASIC by our customers. Also each of design IP is tested on FPGA platform. We use lot of automation for writing Design IP, so time to develop any design IP is very efficient and faster. If you need any design IP which is not listed below, please do let us know. We can develop it very fast for you.

Note : Our Design IP’s are proven in ASIC and FPGA.

List of Design IPs

SmartDV Website

SmartDV on SemiWiki

SmartDV SemiWiki

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