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X-WR-CALDESC:Events for SemiWiki
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BEGIN:VEVENT
DTSTART;VALUE=DATE:20260518
DTEND;VALUE=DATE:20260521
DTSTAMP:20260518T034031
CREATED:20250828T060208Z
LAST-MODIFIED:20250828T060208Z
UID:361093-1779062400-1779321599@semiwiki.com
SUMMARY:VOICE 2026
DESCRIPTION:VOICE is a developer conference\, created by test engineers for test engineers.\n\n\n\n\n\n\n\n\nEach year\, the VOICE Developer Conference unites semiconductor test professionals representing the world’s leading integrated device manufacturers (IDMs)\, foundries\, fabless semiconductor companies and outsourced semiconductor assembly and test (OSAT) providers to exchange information about the latest technology advancements\, express new ideas\, share best practices and network with one another. \n\n\n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/voice-2026/
LOCATION:Scottsdale\, Arizona\, Scottsdale\, AZ\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2025/08/Screenshot-2025-08-27-230026.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260518
DTEND;VALUE=DATE:20260521
DTSTAMP:20260518T034031
CREATED:20260414T061153Z
LAST-MODIFIED:20260414T061153Z
UID:368387-1779062400-1779321599@semiwiki.com
SUMMARY:Surface Preparation and Cleaning Conference (SPCC)
DESCRIPTION:Surface Preparation and Cleaning Conference (SPCC)\, formerly presented by Linx Consulting\, brings together key business insights\, IC manufacturers\, equipment makers\, materials and chemical providers\, metrology experts\, process technologists to address critical challenges\, and innovations in surface preparation and cleaning. \nHeld at the Wild Horse Pass Resort in Chandler\, Arizona\, SPCC 2026 will feature technical sessions\, poster presentations\, and business-focused programming\, creating a unique forum where technology and industry strategy converge. \nREGISTER HERE
URL:https://semiwiki.com/event/surface-preparation-and-cleaning-conference-spcc/
LOCATION:Wild Horse Pass\, Wild Horse Pass\, 5040 Wild Horse Pass Blvd\, Chandler\, AZ\, 85226\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/04/Screenshot-2026-04-13-231044.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260519
DTEND;VALUE=DATE:20260520
DTSTAMP:20260518T034031
CREATED:20260414T060148Z
LAST-MODIFIED:20260414T060148Z
UID:368372-1779148800-1779235199@semiwiki.com
SUMMARY:CadenceCONNECT: Tech Days Europe 2026 - Cambridge
DESCRIPTION:Join us at CadenceCONNECT: Tech Days Europe 2026\, our annual\, free\, multi-track event dedicated to the engineers\, innovators\, and visionaries shaping the future of electronic design. Our aim is to bring together like minded thinkers to explore how AI-driven Cadence technologies are transforming design workflows\, boosting productivity\, and enabling breakthroughs across every domain. \nEvent Details\n06 May 2026 – 30 Jun 2026 \nVarious \nREGISTER HERE
URL:https://semiwiki.com/event/cadenceconnect-tech-days-europe-2026-cambridge/
LOCATION:Cambridge\, UK\, Cambridge\, England\, United Kingdom
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/04/Screenshot-2026-04-13-225642.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260519T090000
DTEND;TZID=America/Los_Angeles:20260519T100000
DTSTAMP:20260518T034031
CREATED:20260505T081403Z
LAST-MODIFIED:20260505T081403Z
UID:369064-1779181200-1779184800@semiwiki.com
SUMMARY:Webinar: Intel: From Construction to Signoff: 3DIC Methodology for Disaggregated Designs
DESCRIPTION:Featured Speaker: \n\nVictoria Kolesov\, Principal Engineer\, Intel\n\nIn this Synopsys webinar\, Intel will present how its disaggregated designs across client and server platforms have driven the evolution of robust 3D multi-die design construction and signoff methodologies. Intel will share practical experience using Synopsys’ complete design implementation and signoff flows for static timing analysis signoff and 3D layout verification in both passive and active interposer designs. The session highlights how increasing accuracy requirements have shaped 3D construction practices\, standards\, and collateral\, enabling consistent\, correct‑by‑construction signoff across process nodes\, TSVs\, and complex die‑to‑die interconnects. \nWhat you’ll learn: \n\nHow Intel approaches 3DIC construction for disaggregated designs\nKey requirements for static timing and layout signoff in 3DIC flows\nDifferences between passive and active interposer signoff considerations\nHow accuracy requirements influence 3D construction methodologies\nBest practices for achieving correct‑by‑construction 3DIC signoff\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nFeatured Speaker\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nVictoria Kolesov \nPrincipal Engineer\, Intel \nVictoria Kolesov joined Intel in 2001 and has held a variety of responsibilities including RTL development\, design completion\, and design automation. Her current focus is interconnect implementation and 3D design integration. Victoria obtained her MS in Computer Science from St.Petersburg Technical University\, Russia. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-intel-from-construction-to-signoff-3dic-methodology-for-disaggregated-designs/
LOCATION:Online
ATTACH;FMTTYPE=image/jpeg:https://semiwiki.com/wp-content/uploads/2026/05/victoria-kolesov-headshotqlt82ampts1777480285645ampresponsiveampfitconstrainampdproff.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260522T100000
DTEND;TZID=America/Los_Angeles:20260522T110000
DTSTAMP:20260518T034031
CREATED:20260414T063003Z
LAST-MODIFIED:20260414T063003Z
UID:368408-1779444000-1779447600@semiwiki.com
SUMMARY:Webinar: How System Scale Expanded\, and Why Network Traffic Validation Became Essential
DESCRIPTION:AI data center networks now operate at a scale where device-level validation no longer reflects real performance. Engineers must understand how systems behave under realistic traffic conditions\, not just in isolated tests. \nJoin Ram Periakaruppan\, vice president and general manager of network applications and security at Keysight\, to learn how large-scale traffic emulation reveals congestion\, latency issues\, and performance limits. You’ll see how to validate AI infrastructure under real workloads and ensure it performs reliably at scale. \nREGISTER HERE
URL:https://semiwiki.com/event/webinar-how-system-scale-expanded-and-why-network-traffic-validation-became-essential/
LOCATION:Online
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260526
DTEND;VALUE=DATE:20260530
DTSTAMP:20260518T034031
CREATED:20260107T103602Z
LAST-MODIFIED:20260107T103602Z
UID:365387-1779753600-1780099199@semiwiki.com
SUMMARY:2026 IEEE 76th Electronic Components and Technology Conference
DESCRIPTION:About ECTC\nThe Electronic Components and Technology Conference (ECTC) is the premier international event that brings together the best in packaging\, components and microelectronic systems science\, technology and education in an environment of cooperation and technical exchange. ECTC is sponsored by the IEEE Electronics Packaging Society. \nREGISTER HERE
URL:https://semiwiki.com/event/2026-ieee-76th-electronic-components-and-technology-conference/
LOCATION:Orlando\, FL\, Orlando\, FL\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/Screenshot-2026-01-07-023521.png
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BEGIN:VEVENT
DTSTART;VALUE=DATE:20260526
DTEND;VALUE=DATE:20260531
DTSTAMP:20260518T034031
CREATED:20260107T103813Z
LAST-MODIFIED:20260107T103813Z
UID:365390-1779753600-1780185599@semiwiki.com
SUMMARY:Hardwear.io Security Trainings and Conference USA 2026
DESCRIPTION:Learn from leading hardware security researchers & professionals and discuss\nthe latest & most innovative research on attacking and defending hardware. \nConnect with industry peers. Join us for a bigger\, bolder\, and better hardwear.io. \nARE YOU READY FOR HARDWEAR.IO USA 2026?\n\nIn the past couple of months our goal was to knuckle down and build a physical event where we can meet again and hang out in a safe & welcoming environment. And we did it! We managed to pull it off\, and (dare we say?) our USA event was incredible. \nBuilding on this success\, Hardwear.io USA returns as a physical conference in Santa Clara Marriott\, USA between 26th May – 30th May 2026. \n26th May – 30th May: fasten your seatbelts for intensive in-person trainings\, top-notch hardware-security talks\, professional networking\, stimulating CTFs and a challenging HardPwn. Mark your calendars and get ready. \nJoin Hardwear.io USA 2026 to learn\, network\, and collaborate with like-minded professionals! \n\nREGISTER HERE
URL:https://semiwiki.com/event/hardwear-io-security-trainings-and-conference-usa-2026/
LOCATION:Santa Clara Marriott\, Santa Clara\, CA\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/Screenshot-2026-01-07-023728.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260527
DTEND;VALUE=DATE:20260528
DTSTAMP:20260518T034031
CREATED:20260414T060317Z
LAST-MODIFIED:20260414T060317Z
UID:368374-1779840000-1779926399@semiwiki.com
SUMMARY:CadenceCONNECT: Tech Days Europe 2026 - Milan
DESCRIPTION:Join us at CadenceCONNECT: Tech Days Europe 2026\, our annual\, free\, multi-track event dedicated to the engineers\, innovators\, and visionaries shaping the future of electronic design. Our aim is to bring together like minded thinkers to explore how AI-driven Cadence technologies are transforming design workflows\, boosting productivity\, and enabling breakthroughs across every domain. \nREGISTER HERE
URL:https://semiwiki.com/event/cadenceconnect-tech-days-europe-2026-milan/
LOCATION:Milan\, Italy\, Milan\, Italy
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/04/Screenshot-2026-04-13-225642.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260528T080000
DTEND;TZID=America/Los_Angeles:20260528T090000
DTSTAMP:20260518T034031
CREATED:20260512T083619Z
LAST-MODIFIED:20260512T083619Z
UID:369183-1779955200-1779958800@semiwiki.com
SUMMARY:Webinar - From Acoustic Wave Filters to RF Front-End Modules: Patent Trends Shaping 5G/6G Connectivity
DESCRIPTION:As 5G and future 6G networks increase RF front-end complexity\, acoustic wave filters and RF front-end modules are facing growing demands for higher frequency operation\, wider bandwidth\, lower losses\, better thermal stability and deeper integration. Based on KnowMade’s latest analyses of RF Acoustic Wave Filters and RF Front-End Modules & Components\, this seminar will explore how patent activity up to 2026 reflects the evolution of competition from discrete acoustic devices to integrated RF front-end architectures. Key topics include SAW\, BAW\, FBAR\, TFSAW\, XBAR\, temperature-compensated filters\, multiplexers\, packaging and module-level integration. \nParticular attention will be given to the evolution of IP leadership between established Japanese and US RF players and fast-rising Chinese entities. While Murata remains the dominant IP leader in RF acoustic wave filters\, companies such as Qualcomm\, Skyworks\, Qorvo\, Taiyo Yuden\, Huawei\, MEMSonics\, Newsonic\, Sanan IC\, RadRock\, ROFS Microsystem and others are shaping a more multipolar competitive landscape. The webinar will also highlight recent patenting activity in 2025 across RF FE segments\, including PA\, LNA\, SAW\, BAW\, RF switches\, tuners\, multiplexers and packaging. \nBy combining patent landscape analysis with annual monitoring insights\, this session will provide a strategic view of where RF front-end innovation is heading\, which players are strengthening their IP positions\, and how emerging technologies may shape the next phase of 5G-Advanced and 6G connectivity. \nPlease log in 15 minutes before the indicated time so as not to miss the beginning of the webinar. \nREGISTER HERE
URL:https://semiwiki.com/event/webinar-from-acoustic-wave-filters-to-rf-front-end-modules-patent-trends-shaping-5g-6g-connectivity/
LOCATION:Online
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/05/Screenshot-2026-05-12-013543.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260528T083000
DTEND;TZID=America/Los_Angeles:20260528T170000
DTSTAMP:20260518T034031
CREATED:20260326T214043Z
LAST-MODIFIED:20260326T214043Z
UID:367930-1779957000-1779987600@semiwiki.com
SUMMARY:TSMC Europe Technology Symposium
DESCRIPTION:Join us to get the latest on:\n\nTSMC’s industry-leading HPC\, Smartphones\, IoT\, and Automotive platform solutions\nTSMC’s advanced logic technology progress on 3nm\, 2nm\, A16\, A14 processes and beyond\nTSMC 3DFabric® advanced silicon stacking and packaging technology advancement on TSMC-SoIC®\, InFO\, CoWoS®\, and TSMC-SoW™\nTSMC’s specialty technology breakthroughs on ultra-low power\, RF\, embedded memory\, power management\, sensor technologies\, and more\nTSMC’s manufacturing excellence\, capacity expansion plans\, and green manufacturing achievements\nTSMC’s Open Innovation Platform® Ecosystem to speed up time-to-design\n\nREGISTER HERE
URL:https://semiwiki.com/event/tsmc-europe-technology-symposium/
LOCATION:Hilton Amsterdam Airport Schiphol\, Hilton Amsterdam Airport Schiphol\, Schiphol Boulevard 701\, 1118 BN Schiphol Airport\, Amsterdam\, Netherlands
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/03/Screenshot-2026-03-26-142210.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260528T100000
DTEND;TZID=America/Los_Angeles:20260528T110000
DTSTAMP:20260518T034031
CREATED:20260425T081459Z
LAST-MODIFIED:20260425T081459Z
UID:368795-1779962400-1779966000@semiwiki.com
SUMMARY:Webinar: Cutting Full-Chip SoC Debug from Days to Minutes with AI
DESCRIPTION:*Company Email Required for Registration* \nFull-chip SoC debug has become one of the most expensive bottlenecks in modern verification. A single production issue can pull multiple engineers away days as they chase a failure through waveforms\, logs\, and across hundreds of thousands of lines of code. \nIn this webinar\, we will demonstrate how the Bronco AI Debug Agent performs root-cause analysis (RCA) on real production issues in under 15 minutes\, with a 70% success rate on customer regressions. You will see the agent operate end-to-end on a representative full-chip SoC\, from a failing regression to an annotated root cause\, while interoperating with customer’s standard commercial EDA flows. \nWhat we will cover: \n– Live demonstration of the Debug Agent on a full-chip SoC regression failure\n– How the agent navigates massive codebases\, logs\, and waveforms to isolate failure mechanisms\n– Deployment patterns at large public chip companies and as well as fast-moving startups\n– How bring-your-own-model and on-prem deployment keep customer IP inside your environment.\n– How Bronco gets better without ever training on customer data. \nWho should attend: \n– DV engineers and managers responsible for regression triage and production debug\n– SoC verification leads evaluating AI-native tooling for their flows\n– VPs of Engineering and Silicon leaders tracking DV cycle time and engineering ROI\n– Security and infrastructure owners assessing on-prem AI deployment for chip design \nSpeaker: \nDavid Zhi LuoZhang\, Co-Founder and CEO of Bronco AI\, will walk through the live demonstration on a real design and take questions how customers deploy\, evaluate\, and scale Bronco within their silicon projects. David works tightly with customers to deploy Bronco and coordinates between the core R&D\, customer\, and industry-relations teams at Bronco. \n*This webinar is in partnership with SemiWiki and Bronco AI* \nREGISTER HERE
URL:https://semiwiki.com/event/webinar-cutting-full-chip-soc-debug-from-days-to-minutes-with-ai/
LOCATION:Online
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/04/Screenshot-2026-04-25-011434.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260529T100000
DTEND;TZID=America/Los_Angeles:20260529T110000
DTSTAMP:20260518T034031
CREATED:20260414T063056Z
LAST-MODIFIED:20260414T063056Z
UID:368410-1780048800-1780052400@semiwiki.com
SUMMARY:Webinar: How Manufacturing Complexity Increased\, and Why Validation Had to Evolve
DESCRIPTION:As semiconductor complexity increases and board designs become denser\, manufacturing teams face tighter tolerances\, reduced test access\, and rising pressure to maintain yield and throughput. Validating RF performance and high-speed digital signal integrity at production scale adds a new layer of complexity that traditional approaches struggle to address. \nJoin Jason Kary\, Senior Vice President and President of Keysight’s Electronic Industrial Solutions Group\, to explore how manufacturing validation is evolving. You’ll learn how wafer-level and in-circuit test strategies improve coverage\, detect defects earlier\, and enable consistent\, high-volume production at scale without compromising quality. \nREGISTER HERE
URL:https://semiwiki.com/event/webinar-how-manufacturing-complexity-increased-and-why-validation-had-to-evolve/
LOCATION:Online
END:VEVENT
END:VCALENDAR