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BEGIN:VEVENT
DTSTART;VALUE=DATE:20260412
DTEND;VALUE=DATE:20260417
DTSTAMP:20260404T044719
CREATED:20260107T100202Z
LAST-MODIFIED:20260107T100202Z
UID:365357-1775952000-1776383999@semiwiki.com
SUMMARY:SPIE Photonics Europe 2026
DESCRIPTION:Hear the latest advances from leading experts. Join colleagues in Strasbourg. \n\nHear research presented at this specialized European event for optical instrumentation with the latest advances in optical systems applications\, materials\, and processing. We look forward to seeing everyone in April. \nRegistration is open. The programme will be available in January. \nConferences: 12–16 April 2026 | Exhibition: 15–16 April 2026 \nAgain this year\, SPIE Photonics Europe 2026 and SPIE Optical Systems Design are co-located. \n\nREGISTER HERE
URL:https://semiwiki.com/event/spie-photonics-europe-2026-2/
LOCATION:Palais de la Musique et des Congrès\, Palais de la Musique et des Congrès\, Place de Bordeaux\, Strasbourg\, 67082\, France
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/DIAMOND-at-SPIE-Photonics-Europe.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260413
DTEND;VALUE=DATE:20260417
DTSTAMP:20260404T044719
CREATED:20260320T200807Z
LAST-MODIFIED:20260320T200807Z
UID:367717-1776038400-1776383999@semiwiki.com
SUMMARY:Failure and Yield Analysis
DESCRIPTION:Failure and Yield Analysis is an increasingly difficult and complex process. Today\, engineers are required to locate defects on complex integrated circuits. In many ways\, this is akin to locating a needle in a haystack\, where the needles get smaller and the haystack gets bigger every year. Engineers are required to understand a variety of disciplines in order to effectively perform failure analysis. This requires knowledge of subjects like: design\, testing\, technology\, processing\, materials science\, chemistry\, and even optics! Failed devices and low yields can lead to customer returns and idle manufacturing lines that can cost a company millions of dollars a day. Your industry needs competent analysts to help solve these problems. Failure and Yield Analysis is a 4-day course that offers detailed instruction on a variety of effective tools\, as well as the overall process flow for locating and characterizing the defect responsible for the failure. This course is designed for every manager\, engineer\, and technician working in the semiconductor field\, using semiconductor components or supplying tools to the industry. \nBy focusing on a Do It Right the First Time approach to the analysis\, participants will learn the appropriate methodology to successfully locate defects\, characterize them\, and determine the root cause of failure. \nWhat Will I Learn By Taking This Class?\nParticipants will learn to develop the skills to determine what tools and techniques should be applied\, and when they should be applied. This skill-building series is divided into three segments: \n\nThe Process of Failure and Yield Analysis. Participants will learn to recognize correct philosophical principles that lead to a successful analysis. This includes concepts like destructive vs. non-destructive techniques\, fast techniques vs. brute force techniques\, and correct verification.\nThe Tools and Techniques. Participants will learn the strengths and weaknesses of a variety of tools used for analysis\, including electrical testing techniques\, package analysis tools\, light emission\, electron beam tools\, optical beam tools\, decapping and sample preparation\, and surface science tools.\nCase Histories. Participants will identify how to use their knowledge through the case histories. They will learn to identify key pieces of information that allow them to determine the possible cause of failure and how to proceed.\n\nCourse Objectives\n\nThis course will provide participants with an in-depth understanding of the tools\, techniques and processes used in failure and yield analysis.\nParticipants will be able to determine how to proceed with a submitted request for analysis\, ensuring that the analysis is done with the greatest probability of success.\nThis course will identify the advantages and disadvantages of a wide variety of tools and techniques that are used for failure and yield analysis.\nThis course will offer a wide variety of video demonstrations of analysis techniques\, so the analyst can get an understanding of the types of results they might expect to see with their equipment.\nParticipants will be able to identify basic technology features on semiconductor devices.\nParticipants will be able to identify a variety of different failure mechanisms and how they manifest themselves.\nParticipants will be able to identify appropriate tools to purchase when starting or expanding a laboratory.\n\nREGISTER HERE
URL:https://semiwiki.com/event/failure-and-yield-analysis/
LOCATION:Phoenix\, AZ\, Phoenix\, AZ\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/03/Screenshot-2026-03-20-130723.png
ORGANIZER;CN="Semitracks%2C Inc.":MAILTO:info@semitracks.com
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260414
DTEND;VALUE=DATE:20260417
DTSTAMP:20260404T044719
CREATED:20260304T225338Z
LAST-MODIFIED:20260304T225338Z
UID:367187-1776124800-1776383999@semiwiki.com
SUMMARY:2026 CMC Conference
DESCRIPTION:2026 CMC Conference\nApril 14-16\, 2026\n“Critical Materials at the Crossroads— \nDriving the Roadmap for Semiconductor Materials” \nDoubleTree by Hilton Hotel in Portland\, Oregon \nFeaturing Keynote: \nBen Sell\, Vice President and GM of Logic Technology Development at Intel Corporation \n*The CMC Conference follows the Private CMC Meetings: \nCMC Fabs-Only on Apr. 13-14 and CMC Joint Session (Fabs & Suppliers) on Apr. 14 \nThe Critical Materials Council (CMC) Conference\, brought to you by TECHCET\, is a two-day event designed to deliver actionable insights into the materials and supply chains that enable today’s and tomorrow’s semiconductor manufacturing. The program focuses on the critical materials that drive innovation\, strengthen industry resiliency\, and support long-term sustainability across the global semiconductor ecosystem. Unlike other conferences\, the CMC Conference provides practical information addressing “How-to” not just “What.” Solutions to process challenges and materials-related issues are a key focus for the CMC conference presenters. Equally important focal points include business and supply-chain trends and materials needed for emerging technologies. \nFeaturing 5 Impactful Sessions:\n1. Global Issues & Trends Impacting Materials\n2. Immediate Issues of Manufacturing and Materials\n3. Heterogenous Integration & Advanced Packaging Materials\n4. Challenges of Equipment & Component Materials\n5. Emerging Materials in R&D and Pilot Fabrication \nREGISTER HERE
URL:https://semiwiki.com/event/2026-cmc-conference/
LOCATION:DoubleTree by Hilton Hotel Portland\, DoubleTree by Hilton Hotel Portland\, 1000 NE Multnomah St\, Portland\, OR\, 97232\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/03/2026-conference-banner-register-today.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260416
DTEND;VALUE=DATE:20260417
DTSTAMP:20260404T044719
CREATED:20260107T100524Z
LAST-MODIFIED:20260107T100524Z
UID:365360-1776297600-1776383999@semiwiki.com
SUMMARY:CadenceLIVE Silicon Valley 2026
DESCRIPTION:Join us on April 16 for CadenceLIVE Silicon Valley 2026\, where Cadence technology users connect with the engineers and industry leaders who develop the solutions and the industry experts who influence market trends. \nParticipants experience a day of learning\, connection\, and cutting-edge technology shaping the future of electronic design and intelligent systems. This premier event brings together the brightest minds for a day of inspiration and innovation. \nREGISTER HERE
URL:https://semiwiki.com/event/cadencelive-silicon-valley-2026/
LOCATION:Santa Clara Convention Center\, Santa Clara Convention Center\, 5001 Great America Pkwy\, Santa Clara\, CA\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/Screenshot-2026-01-07-020502.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260419
DTEND;VALUE=DATE:20260424
DTSTAMP:20260404T044719
CREATED:20260107T100748Z
LAST-MODIFIED:20260107T100748Z
UID:365363-1776556800-1776988799@semiwiki.com
SUMMARY:2026 IEEE Custom Integrated Circuits Conference (CICC)
DESCRIPTION:Join us for CICC 2026\, the world’s premier conference devoted to IC development. \n\n\n\n\n\n\nApril 19 – 22\, 2026 Seattle\, WA\, USA \n\n\n\n\n\n\nApril 22 – 23\, 2026 – CHISIC Workshop \nAbout CICC\n\n\nThe IEEE Custom Integrated Circuits Conference is a premier conference devoted to IC development. The conference program is a blend of oral presentations\, exhibits\, panels and forums. The conference sessions present original first published technical work and innovative circuit techniques that tackle practical problems. CICC is the conference to find out how to solve design problems\, improve circuit design techniques\, get exposure to new technology areas\, and network with peers\, authors and industry experts. \nThere are 3 days of Technical Sessions that include lecture presentations addressing state of the art developments in integrated circuit design. The Educational Sessions are a full day of tutorials instructed by recognized invited speakers. The Panels\, and Forums are presented throughout the conference to enrich the learning experience of the attendees. The Panel Discussions and Forums are presented by leaders from the IC industry. CICC includes an Exhibits Hall that is open in the evenings where Semiconductor manufacturers\, software tool suppliers\, silicon IP providers\, design-service houses\, and technical book publishers offer displays and demonstrations of their products. CICC is sponsored by the IEEE Solid-State Circuits Society and technically co-sponsored by the IEEE Circuits and Systems Society. \n\n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/2026-ieee-custom-integrated-circuits-conference-cicc/
LOCATION:Seattle\, Washington\, Seattle\, WA\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/Screenshot-2026-01-07-020639.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260420
DTEND;VALUE=DATE:20260423
DTSTAMP:20260404T044719
CREATED:20250828T055712Z
LAST-MODIFIED:20250828T055712Z
UID:361084-1776643200-1776902399@semiwiki.com
SUMMARY:DATE 2026
DESCRIPTION:Design\, Automation and Test in Europe Conference |\nThe European Event for Electronic System Design & Test\nCall for Papers\n\n\nThe DATE conference is the main European event bringing together designers and design automation users\, researchers and vendors\, as well as specialists in hardware and software design\, test\, and manufacturing of electronic circuits and systems. DATE places a strong emphasis on both technology and systems\, covering ICs/SoCs\, reconfigurable hardware\, and embedded systems\, as well as embedded software. \nThe three-day event consists of a conference with regular papers\, extended abstracts\, and late breaking results\, complemented by timely keynotes\, special days\, focus sessions\, embedded tutorials\, half-day workshops\, and multi-partner project sessions. The event will also host the Young People Programme fostering networking and exchanges of information on relevant issues\, recent research outcomes\, and career opportunities for junior researchers. Poster-supported live interactions and pre-recorded videos are available to complement all research paper presentations before\, during\, and after the conference. \nDATE 2026 is the 29th edition of an event that has always been the place for researchers\, young professionals\, and industrial partners to meet\, present their research\, and discuss current developments and upcoming trends\, with high emphasis on social interaction. \nConference Scope\nThe conference addresses all aspects of research into technologies for electronic and systems engineering. It covers the design process\, test\, and tools for design automation of electronic products\, ranging from integrated circuits to distributed large-scale systems. This domain includes both hardware and embedded software design issues. The conference scope also includes the specification of design requirements and new architectures for challenging application fields such as sustainable computing\, smart societies and digital wellness\, secure systems\, autonomous systems and smart industry\, and state-of-the-art applications of artificial intelligence. Engineers\, scientists\, and researchers involved in innovative industrial designs are particularly encouraged to submit papers to foster feedback ranging from design to research aspects. \nConference Sponsors\nThe event is sponsored by the European Design and Automation Association (EDAA)\, the Electronic System Design Alliance (ESDA)\, the IEEE Council on Electronic Design Automation (IEEE CEDA) and the ACM Special Interest Group on Design Automation (ACM SIGDA). \nIn cooperation with IEEE Computer Society Test Technology Technical Community (TTTC)\, IEEE Solid-State Circuits Society (SSCS) and IEEE Computer Society (IEEE CS). \nConference Committees\nThe conference leverages the support of multiple committees to support its organisation. The DATE Sponsors Committee supervises the overall structure and operations of the conference; the Executive Committee designs and implement the yearly programme of the conference\, and the Technical Programme Committee is dedicated to develop reviews and select the research manuscripts to be published at the conference. \n\nDATE Sponsors Committee (DSC)\nDATE Executive Committee (DEC)\nTechnical Programme Committee (TPC)\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/date-2026/
LOCATION:Palazzo della Gran Guardia\, Palazzo della Gran Guardia\, Piazza Brà\, Verona\, 37121\, Italy
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2025/08/Screenshot-2025-08-27-225522.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260420
DTEND;VALUE=DATE:20260424
DTSTAMP:20260404T044719
CREATED:20260320T201032Z
LAST-MODIFIED:20260320T201032Z
UID:367720-1776643200-1776988799@semiwiki.com
SUMMARY:Semiconductor Reliability and Product Qualification
DESCRIPTION:Product reliability and qualification continues to evolve with the electronics industry. New electronics applications require new approaches to reliability and qualification. In the past\, reliability meant discovering\, characterizing and modeling failure mechanisms\, and determining their impact on the reliability of the circuit. Today\, reliability can involve tradeoffs between performance and reliability; assessing the impact of new materials; dealing with limited margins\, and other factors. This requires information on subjects like: statistics\, testing\, technology\, processing\, materials science\, chemistry\, and customer expectations. While customers expect high reliability levels\, incorrect testing\, calculations\, and qualification procedures can severely impact reliability. Semiconductor Reliability and Product Qualification is a 4-day course that offers detailed instruction on a variety of subjects pertaining to semiconductor reliability and qualification. This course is designed for every manager\, engineer\, and technician concerned with reliability in the semiconductor field\, qualifying semiconductor components\, or supplying tools to the industry. \nWhat Will I Learn By Taking This Class?\nParticipants will learn to develop the skills to determine what failure mechanisms might occur\, and how to test for them\, develop models for them\, and eliminate them from the product. This skill building series is divided into four segments: \n\nOverview of Reliability and Statistics. Participants will learn the fundamentals of statistics\, sample sizes\, distributions and their parameters.\nFailure Mechanisms. Participants will learn the nature and manifestation of a variety of failure mechanisms that can occur both at the die and at the package level. These include: time-dependent dielectric breakdown\, hot carrier degradation\, electromigration\, stress-induced voiding\, moisture\, corrosion\, contamination\, thermomechanical effects\, interfacial fatigue\, and others.\nQualification Principles. Participants will learn how test structures can be designed to help test for a particular failure mechanism.\nTest Strategies. Participants will learn about the JEDEC test standards\, how to design screening tests\, and how to perform burn-in testing effectively.\n\nCourse Objectives\n\nThis course will provide participants with an in-depth understanding of the failure mechanisms\, test structures\, equipment\, and testing methods used to achieve today’s high reliability components.\nParticipants will be able to gather data\, determine how best to plot the data and make inferences from that data.\nThis course will identify the major failure mechanisms\, explain how they are observed\, how they are modeled\, and how they are eliminated.\nThis course will offer a variety of video demonstrations of analysis techniques\, so the participants can get an understanding of the types of results they might expect to see with their equipment.\nParticipants will be able to identify the steps and create a basic qualification process for semiconductor devices.\nParticipants will be able to knowledgeably implement screens that are appropriate to assure the reliability of a component.\nParticipants will be able to identify appropriate tools to purchase when starting or expanding a laboratory.\n\nREGISTER HERE
URL:https://semiwiki.com/event/semiconductor-reliability-and-product-qualification/
LOCATION:San Jose\, CA
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/03/Screenshot-2026-03-20-130723.png
ORGANIZER;CN="Semitracks%2C Inc.":MAILTO:info@semitracks.com
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260421T090000
DTEND;TZID=America/Los_Angeles:20260421T100000
DTSTAMP:20260404T044719
CREATED:20260401T065505Z
LAST-MODIFIED:20260401T065640Z
UID:368025-1776762000-1776765600@semiwiki.com
SUMMARY:Webinar: Understanding UALink Architecture: A Protocol Deep Dive
DESCRIPTION:As AI workloads scale into the thousands of accelerators and hundreds of terabytes of distributed memory\, traditional interconnects cannot deliver the deterministic latency\, bandwidth efficiency\, or memory semantic operations required for modern training clusters. UALink provides a purpose built accelerator fabric leveraging 224G SerDes\, fixed 64 byte flits\, compressed transaction formats\, and high efficiency TL/DLL aggregation to achieve predictable\, low overhead load/store communication across large GPU pools. With multi virtual channel flow control\, source ordered routing\, and integrated AES GCM encryption via UALinkSec\, the architecture is engineered for high performance\, secure AI fabrics. \nThis session will review a breakdown of how UALink enables scalable memory pooling\, reduces communication overhead\, and supports pod  and rack scale GPU integration. We will examine the behavior of the UPLI\, Transaction Layer\, and Data Link Layer and discuss silicon level implementation considerations for accelerators and switches. \nWhat you’ll learn: \n\nHow UALink implements low latency\, memory semantic GPU to GPU communication\nInternal structure of 64 byte flits\, compressed request/response formats\, and TL/DLL packing\nHow multi VC flow control\, link level retry\, and RS FEC ensure deterministic\, lossless throughput\nThe role of UALinkSec in enforcing end to end AES GCM encryption and authentication\nHow UALink enables scalable memory pooling and GPU clustering across pods and racks\nSystem level design considerations for integrating UALink controllers\, PHYs\, and switches\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nFeatured Speaker\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nDiwakar Kumaraswamy \nSr. Staff Technical Product Manager \nWith over 15 years of experience in Application Engineering and SoC design\, Diwakar has built a career spanning FPGA development\, global IP support\, and technical leadership. Beginning at CoreEL Technologies with Xilinx FPGA implementations and corporate training\, he went on to lead customer success for PCIe\, CXL\, AMBA\, and other interface IP at Synopsys\, followed by NoC architecture work at Intel. Now a Technical Product Manager at Synopsys\, he drives high-speed interconnect solutions—such as Ethernet\, PCIe\, and UALink—for next-generation AI infrastructure. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-understanding-ualink-architecture-a-protocol-deep-dive/
LOCATION:Online
ATTACH;FMTTYPE=image/jpeg:https://semiwiki.com/wp-content/uploads/2026/03/Synopsys-understanding-ualink-architecture-webinar-1200x628-1.jpeg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260422T083000
DTEND;TZID=America/Los_Angeles:20260422T173000
DTSTAMP:20260404T044719
CREATED:20260326T212327Z
LAST-MODIFIED:20260326T212327Z
UID:367920-1776846600-1776879000@semiwiki.com
SUMMARY:TSMC 2026 North America Technology Symposium
DESCRIPTION:Join us to get the latest on:\n\nTSMC’s industry-leading HPC\, Smartphones\, IoT\, and Automotive platform solutions\nTSMC’s advanced logic technology progress on 3nm\, 2nm\, A16\, A14 processes and beyond\nTSMC 3DFabric® advanced silicon stacking and packaging technology advancement on TSMC-SoIC®\, InFO\, CoWoS®\, and TSMC-SoW™\nTSMC’s specialty technology breakthroughs on ultra-low power\, RF\, embedded memory\, power management\, sensor technologies\, and more\nTSMC’s manufacturing excellence\, capacity expansion plans\, and green manufacturing achievements\nTSMC’s Open Innovation Platform® Ecosystem to speed up time-to-design\n\nREGISTER HERE
URL:https://semiwiki.com/event/tsmc-2026-north-america-technology-symposium/
LOCATION:Santa Clara Convention Center\, Santa Clara Convention Center\, 5001 Great America Pkwy\, Santa Clara\, CA\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/03/Screenshot-2026-03-26-142210.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260426
DTEND;VALUE=DATE:20260502
DTSTAMP:20260404T044719
CREATED:20260107T101053Z
LAST-MODIFIED:20260107T101053Z
UID:365366-1777161600-1777679999@semiwiki.com
SUMMARY:2026 MRS Spring Meeting & Exhibit
DESCRIPTION:The 2026 MRS Spring Meeting & Exhibit\, taking place April 26–May 1 in Honolulu\, Hawai‘i\, will convene materials researchers from academia\, industry\, government and national laboratories together for a week of cross-disciplinary collaboration and scientific exchange. Set against the backdrop of one of MRS’s most inspiring locations\, the Meeting & Exhibit will feature breakthroughs in areas such as sustainable manufacturing\, advanced characterization and energy materials—driving forward innovation on a global scale. \nBuilding on this inspiring setting\, the Meeting will span four official venues in Honolulu. Technical programming\, events and accommodations will be distributed within the city’s walkable\, picturesque layout\, creating a dynamic\, interconnected format that will support active engagement and collaboration while maintaining a focused environment for research and application dialogue throughout the Meeting week. \nWhether you’re looking to present new research\, explore emerging technologies\, or engage with peers across disciplines\, the 2026 MRS Spring Meeting will provide an unforgettable experience in an extraordinary location. \nREGISTER HERE
URL:https://semiwiki.com/event/2026-mrs-spring-meeting-exhibit/
LOCATION:Honolulu\, Hawaii\, Honolulu\, HI\, United States
ATTACH;FMTTYPE=image/jpeg:https://semiwiki.com/wp-content/uploads/2026/01/1758156481328.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260428
DTEND;VALUE=DATE:20260429
DTSTAMP:20260404T044719
CREATED:20260107T101352Z
LAST-MODIFIED:20260107T101352Z
UID:365369-1777334400-1777420799@semiwiki.com
SUMMARY:User2User North America 2026
DESCRIPTION:Join us for the User2User North America event\, which is a dedicated environment for exchanging ideas\, information and best practices that enable you to lead in your role and achieve success with your customers. \nBecome a Speaker\nAbout User2User\nUser2User is your opportunity to learn\, grow and connect with fellow technical experts who design leading-edge products using Siemens electronic design automation (EDA) tools. \nWhat to expect?\nA dedicated environment for exchanging ideas\, information\, and best practices that enable you to lead in your role and achieve success with your customers. \n\nTechnical agenda concentrated on the digital future\nIndustry leaders exploring macro trends and innovation\nSuper users sharing business challenges and roadblocks\nCase studies demonstrating business results\nNetworking with like-minded peers in EDA\n\nREGISTER HERE
URL:https://semiwiki.com/event/user2user-north-america-2026/
LOCATION:Santa Clara Marriott\, Santa Clara\, CA\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/Screenshot-2026-01-07-021240.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260429
DTEND;VALUE=DATE:20260501
DTSTAMP:20260404T044719
CREATED:20260107T101637Z
LAST-MODIFIED:20260107T101637Z
UID:365373-1777420800-1777593599@semiwiki.com
SUMMARY:SEMIEXPO Heartland
DESCRIPTION:FOCUSED ON SMART MANUFACTURING & SMART MOBILITY\n\n\nDRIVING SEMICONDUCTOR BUSINESS IN THE MIDWEST \nThank you for being part of the launch of SEMIEXPO Heartland—where Smart Manufacturing and Smart Mobility came together like never before! This groundbreaking event opened new opportunities for collaboration and growth\, driving us toward the semiconductor industry’s $1T future. \nWith so much innovation concentrated in the Midwest\, SEMIEXPO Heartland is just getting started. Stay tuned for our next chapter in Spring 2026—we’ll see you in Detroit\, MI! Get ready for even more inspiration\, insights\, and connections at the intersection of two critical markets. \nMAKE AN IMPACT AT THE INAUGURAL SEMIEXPO HEARTLAND \nPlan Now to Exhibit or Sponsor. Contact—\nShane Poblete | +1 202-847-5983 | spoblete@semi.org \n\n\n\n\n2025 Post Show Report\n\n\n\n\n\n\n\nAnalytics & Statistics\nAttendee Demographics\nKeynotes\nProgram Highlights\nAnd more!\n\n\n\n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/semiexpo-heartland/
LOCATION:Detroit Marriott at the Renaissance Center\, 400 Renaissance Dr W\, Detroit\, MI\, 48243\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/Screenshot-2026-01-07-021542.png
END:VEVENT
END:VCALENDAR