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Register for CadenceTECHTALK to find out how to achieve verification closure with the same coverage with up to a 10X reduction in simulation cycles.
Chips are becoming bigger and more complex, adding to already existing verification woes. Design and verification engineers struggle with running billions of regression cycles… Read More
Date: Tuesday, December 13, 2022
Time: 09:00 GMT / 10:00 CET / 11:00 EET & Israel / 14:30 IST
Simulator performance is critical owing to the exponentially increasing complexity of SoC designs and shrinking market time. Cadence® Xcelium™ is a leader in simulation performance, and we focus relentlessly on improving the core… Read More
Machine learning (ML) is finding its way into many of the tools in silicon design flows, to shorten run times and improve the quality of results. Logic simulation seemed an obvious target for ML, though resisted apparent benefits for a while. I suspect this was because we all assumed the obvious application should be to use ML to refine… Read More
Date: Wednesday, September 21, 2022
Time: 9:00am – 10:00am PDT
Register for this CadenceTECHTALK if you are looking for an end-to-end solution for all your verification requirements in automotive, mobile, and hyperscale designs.
This CadenceTECHTALK introduces Xcelium Apps, a portfolio of domain-specific technologies… Read More
Date: Thursday, September 29, 2022
Time: 09:00 BST / 10:00 CEST / 11:00 EEST and Israel
Crack the Verification Double Trouble! Chips are becoming bigger and more complex, adding to already existing verification woes. Design and verification engineers struggle with running billions of regression cycles to achieve the desired
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Overview
High-performance DFT simulation is key to completing today’s complex systems on chip (SoCs) on schedule. Because most simulators were developed before the multi-core era, they process Verilog code in a single thread, managing a single active queue of events and handling them one at a time. The serial method in
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I imagine that the title of this post will remind many of 80s synth-pop, or perhaps the movie The Breakfast Club. But my topic is the venerable hardware verification language (HVL) known simply as e. It has quite an interesting history and it played a key role in the development of the modern testbench methodology that most chip verification… Read More
SoC verification has always been an interesting topic for me. Having worked at companies like Zycad that offered hardware accelerators for logic and fault simulation, the concept of reducing the time needed to verify a complex SoC has occupied a lot of my thoughts. The bar we always tried to clear was actually simple to articulate… Read More
