Webinar: Real-time In-Chip Monitoring to Boost multi-core AI, ML, DL Systems

Webinar: Real-time In-Chip Monitoring to Boost multi-core AI, ML, DL Systems
by Daniel Payne on 04-28-2020 at 10:00 am

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During the COVID-19 pandemic I’m using Zoom and attending more webinars to keep updated on semiconductor industry trends, and one huge trend is the importance of AI applied to SoCs. Using more cores to handle ML and DL makes sense, but then how do you keep the chips within their power and reliability limits while at the same … Read More


WEBINAR: Silicon Valley the Way I Saw It (Semiconductor History)

WEBINAR: Silicon Valley the Way I Saw It (Semiconductor History)
by Daniel Nenni on 04-26-2020 at 5:39 am

Today people make chips with 10 billion transistors and no-one thinks anything of it. But there was a day (Or more correctly a decade) when we couldn’t make even one transistor reliably. How did we start there and get where we are today? Who were the players? What did they do? John East is a grizzled veteran of the semiconductor business.… Read More


License-first Scheduling for High-throughput Computing

License-first Scheduling for High-throughput Computing
by Admin on 04-10-2020 at 1:43 pm

Saving Serious Money With License-first Scheduling for High-throughput Computing

Live Webinar – Tuesday | April 21st | 2pm ET (11am PDT)

Make Your Infrastructure Work Harder with License-first Scheduling

Computer hardware and software never get tired and never need a lunch break. Ideally you’d like to use them 24/7 –

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Concurrent Electro-Thermal Analysis of PowerMOS Devices to Improve Performance and Reliability

Concurrent Electro-Thermal Analysis of PowerMOS Devices to Improve Performance and Reliability
by Admin on 04-09-2020 at 1:27 pm

Click Here to Register to View the Video

PowerMOS devices play a major role in a variety of power converter and control circuits. Some examples of their applications include PMICs or boost and buck converters. Often these are used in mobile and IoT devices to convert battery voltages to circuit operating voltages. Analysis tools… Read More


Prevent and Eliminate IR drop and Power Integrity Issues using Redhawk Analysis Fusion

Prevent and Eliminate IR drop and Power Integrity Issues using Redhawk Analysis Fusion
by Admin on 03-14-2020 at 2:44 am

Tue, Mar 31, 2020 11:00 AM – 12:00 PM MDT

*** This webinar requires that you register with your work email address ***

As we move towards advanced nodes where supply voltage reduces and transistors shrink in size, reliability challenges increase significantly. Designers see more IR drop and power integrity issues, and we… Read More


Analog IP Migration, Optimization and Verification

Analog IP Migration, Optimization and Verification
by Admin on 03-14-2020 at 2:42 am

Thu, Mar 26, 2020 11:00 AM – 12:00 PM MDT

** Work email address required**

ABSTRACT: Semiconductor companies designing ICs for smart phones, automotive and industrial applications, CPUs, GPUs and memory components all employ teams of custom IC designers to create the highest performance chips that are as small as possible,… Read More


Achieving Design Robustness in Signoff for Advanced Node Digital Designs

Achieving Design Robustness in Signoff for Advanced Node Digital Designs
by Admin on 03-14-2020 at 2:40 am

Tue, Mar 24, 2020 11:00 AM – 12:00 PM MDT

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As designs migrate to cutting edge single digit nanometer technologies, designing high yielding products that quickly enter the market is key to remain competitive in the chip industry. Advanced node digital… Read More


Chip-to-Chip Communication (Interlaken-LL) for Enterprise and Cloud

Chip-to-Chip Communication (Interlaken-LL) for Enterprise and Cloud
by Admin on 03-14-2020 at 2:39 am

Thu, Mar 19, 2020 11:00 AM – 12:00 PM MDT

** Work email address required**
Interlaken chip-to-chip connectivity IP has been used for many years in networking and switching fabrics to move high throughput data between large chips. With advanced technology nodes, increasing chip sizes and CPU cluster-based designs, Interlaken
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Six Automated Steps to Design Partitioning for Multi-FPGA Prototyping Boards

Six Automated Steps to Design Partitioning for Multi-FPGA Prototyping Boards
by Admin on 03-14-2020 at 2:36 am

Tue, Mar 17, 2020 11:00 AM – 12:00 PM MDT

** Work email address required**
ABSTRACT
Presently, emulation and FPGA-based prototyping are essential verification and validation techniques for a SoC, ASIC designs and become irreplaceable in pre-silicon verification of Deep Learning Accelerator designs. Challenges of
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Concept Modeling: Design Exploration for Every Engineer

Concept Modeling: Design Exploration for Every Engineer
by Admin on 03-10-2020 at 9:15 pm

May 12, 2020

11:00 AM (EDT)

Venue:
Online

This webinar will describe how ANSYS Discovery is replacing traditional CAD technologies with direct editing and a modern UI that is fast, easy and intuitive to learn. Discovery can import, repair and modify files from any CAD system, including the native CAD files or the generic files used

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