CadenceTECHTALK: Soar to New Heights of Productivity using Cadence Managed Cloud Services

CadenceTECHTALK: Soar to New Heights of Productivity using Cadence Managed Cloud Services
by Admin on 10-04-2023 at 4:42 am

Time:

10:00 am China, Singapore, Taiwan
11:00 am Japan, Korea

Join us for this 45-minute webinar to learn how the Cadence-managed, EDA-optimized, ready-to-use, and secure ISO-certified cloud platform delivers a fully integrated and proven environment to jump-start product design, verification, and implementation. See

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Webinar: UCIe-Based Chiplet Verification – from IP to SoC

Webinar: UCIe-Based Chiplet Verification – from IP to SoC
by Admin on 09-15-2023 at 12:15 pm

About

Innovative die disaggregation technologies, enable a future where a catalog of chiplets will be available to mix and match based on the end application. The industry’s fastest emerging interconnect standard called Universal Chiplet Interconnect Express (UCIe) enables end users to combine chiplets with different functionality… Read More


CadenceTECHTALK: Proactively Address Thermal Concerns in Advanced IC Packages

CadenceTECHTALK: Proactively Address Thermal Concerns in Advanced IC Packages
by Admin on 08-31-2023 at 2:42 pm

Date: Thursday, October 12, 2023

Time: 10:00am – 11:00am (PDT)

The heterogeneous integration of chips and chiplets in IC packages is all the rage as we face “More than Moore” performance challenges. While these innovative design practices successfully address performance goals, some design teams find that IC packages… Read More


Stratus HLS (High Level Synthesis) Seminar Series [Part 2]: SystemC simulation and debugging

Stratus HLS (High Level Synthesis) Seminar Series [Part 2]: SystemC simulation and debugging
by Admin on 08-31-2023 at 2:05 pm

Date: September 15, 2023 (Friday) 15:00-16:00

Organizer:

Cadence Design Systems Japan
Innotech Co., Ltd. IC Solution Division

Cost: Free

Venue: Online (Zoom webinar)

* It is also possible to participate from a web browser.

We recommend using Google Chrome, Firefox, or Chromium Edge.

Registration deadline: September 14th

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Latest Virtuoso Studio & Specter Function Introduction Seminar

Latest Virtuoso Studio & Specter Function Introduction Seminar
by Admin on 08-31-2023 at 1:34 pm

As processes become finer and circuits become more complex, analog design becomes more and more difficult, requiring even greater efficiency and automation.

In this seminar, we will introduce solutions for solving design issues incorporated in the latest versions of the analog/mixed-signal IC design environment Virtuoso… Read More


CadenceTECHTALK: High-Speed Channel Signal Integrity Optimization

CadenceTECHTALK: High-Speed Channel Signal Integrity Optimization
by Admin on 07-26-2023 at 3:22 pm

Date: Tuesday, August 29, 2023

Time: 10:00am PDT | 1:00pm EDT

Join our webinar as we share new optimization techniques to improve the efficiency and performance of your designs. The Optimality™ Explorer in the the Clarity™ 3D workbench allows users to navigate the design space with a panoramic view that can compensate for many… Read More


CadenceTECHTALK: The ABCs (Achieving Better Components) of RF Optimization

CadenceTECHTALK: The ABCs (Achieving Better Components) of RF Optimization
by Admin on 07-25-2023 at 2:58 pm

Date: Tuesday, August 15, 2023

Time: 10:00am – 11:00am (PDT)

The new intelligent, Pointer-Hybrid optimization algorithm in the latest release of Microwave Office software provides fast and robust design space exploration. Furthermore, this new optimization technology can be combined with Cadence’s advanced computational

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Cadence TECHTALK: Solution for 3D-IC Interposer Signal Integrity

Cadence TECHTALK: Solution for 3D-IC Interposer Signal Integrity
by Admin on 07-12-2023 at 3:31 pm

Date: Wednesday, July 26, 2023

Time: 10:00am PDT | 1:00pm EDT

3D-IC design requires early analysis of thermal properties, power delivery, and signal integrity. This webinar will work through the process of simulating heterogeneously integrated chiplets. Learn about the integrated workflow that begins with silicon design… Read More


CadenceTECHTALK: Automated Verification for Cache Coherent RISC-V SoCs

CadenceTECHTALK: Automated Verification for Cache Coherent RISC-V SoCs
by Admin on 06-23-2023 at 1:05 pm

Date: Tuesday, July 18, 2023

Time: 11:00 AM PDT | 1:00 PM CDT | 2:00 PM EDT

RISC-V SoC design complexity continues to increase and create new verification challenges. Private caches, shared caches, and shared main memory create potential caches/memory coherency problems that require modern, automated verification approaches.… Read More


Webinar: An AI/ML Driven High-Level Synthesis Solution

Webinar: An AI/ML Driven High-Level Synthesis Solution
by Admin on 06-20-2023 at 4:16 pm

High-Level Synthesis (HLS) tools yield better PPA when the “right set” of optimization constraints and tool settings are applied. Determining the right set of constraints and settings requires design and tool experience and exploration. AI/ML technology has proven highly effective at exploring the solution… Read More