Tag: techtalk
Webinar: UCIe-Based Chiplet Verification – from IP to SoC
About
Innovative die disaggregation technologies, enable a future where a catalog of chiplets will be available to mix and match based on the end application. The industry’s fastest emerging interconnect standard called Universal Chiplet Interconnect Express (UCIe) enables end users to combine chiplets with different functionality… Read More
CadenceTECHTALK: Proactively Address Thermal Concerns in Advanced IC Packages
Date: Thursday, October 12, 2023
Time: 10:00am – 11:00am (PDT)
The heterogeneous integration of chips and chiplets in IC packages is all the rage as we face “More than Moore” performance challenges. While these innovative design practices successfully address performance goals, some design teams find that IC packages… Read More
Stratus HLS (High Level Synthesis) Seminar Series [Part 2]: SystemC simulation and debugging
Latest Virtuoso Studio & Specter Function Introduction Seminar
As processes become finer and circuits become more complex, analog design becomes more and more difficult, requiring even greater efficiency and automation.
In this seminar, we will introduce solutions for solving design issues incorporated in the latest versions of the analog/mixed-signal IC design environment Virtuoso… Read More
CadenceTECHTALK: High-Speed Channel Signal Integrity Optimization
Date: Tuesday, August 29, 2023
Time: 10:00am PDT | 1:00pm EDT
Join our webinar as we share new optimization techniques to improve the efficiency and performance of your designs. The Optimality™ Explorer in the the Clarity™ 3D workbench allows users to navigate the design space with a panoramic view that can compensate for many… Read More
CadenceTECHTALK: The ABCs (Achieving Better Components) of RF Optimization
Cadence TECHTALK: Solution for 3D-IC Interposer Signal Integrity
Date: Wednesday, July 26, 2023
Time: 10:00am PDT | 1:00pm EDT
3D-IC design requires early analysis of thermal properties, power delivery, and signal integrity. This webinar will work through the process of simulating heterogeneously integrated chiplets. Learn about the integrated workflow that begins with silicon design… Read More
CadenceTECHTALK: Automated Verification for Cache Coherent RISC-V SoCs
Date: Tuesday, July 18, 2023
Time: 11:00 AM PDT | 1:00 PM CDT | 2:00 PM EDT
RISC-V SoC design complexity continues to increase and create new verification challenges. Private caches, shared caches, and shared main memory create potential caches/memory coherency problems that require modern, automated verification approaches.… Read More
Webinar: An AI/ML Driven High-Level Synthesis Solution
High-Level Synthesis (HLS) tools yield better PPA when the “right set” of optimization constraints and tool settings are applied. Determining the right set of constraints and settings requires design and tool experience and exploration. AI/ML technology has proven highly effective at exploring the solution… Read More