Aldec reprograms HES7 for AXI4 speed

Aldec reprograms HES7 for AXI4 speed
by Don Dingee on 02-26-2016 at 4:00 pm

FPGA-based prototyping firms are all grappling with the problem of higher speed connectivity between a development host and their hardware. Aldec is announcing their solution at DVCon 2016, turning to an AMBA AXI4 interface bridged into a host with PCIe x8.

Faster host interfaces deliver dual benefits in FPGA-based prototyping.… Read More


HW/SW Interfaces for Portable Stimulus

HW/SW Interfaces for Portable Stimulus
by Pawan Fangaria on 02-26-2016 at 12:00 pm

With growing size and complexity of SoC, the semiconductor community is realizing the growing pain of verification. The cost of SoC verification grows exponentially with design size. Moreover, there is no single methodology for verifying a SoC; multiple engines are used in different contexts through different verification… Read More


Synopsys at DVCon 2016

Synopsys at DVCon 2016
by Bernard Murphy on 02-23-2016 at 12:00 pm

It’s that time of year again – DVCon starts on Monday Feb 29[SUP]th[/SUP] and as always should be a packed event. Synopsys plans a big showing, in the exhibit hall, in a sponsored lunch, at tutorials and in papers. Time to get your conference shoes on and go check them out – I plan to be there all week.

One of the most obvious things you will… Read More


Coming to a Workstation Near You: Accellera’s Portable Stimulus Standard

Coming to a Workstation Near You: Accellera’s Portable Stimulus Standard
by Ellie Burns on 11-29-2015 at 7:00 am

Portable Stimulus has become such a popular standards topic of late that I thought it would be good to take a break this month from my low power series to bring you, my valued readers, more information about it from one of my colleagues, Dennis Brophy, who is working to help drive development of this standard within Accellera. I’ll Read More


Moving up Verification to Scenario Driven Methodology

Moving up Verification to Scenario Driven Methodology
by Pawan Fangaria on 09-11-2015 at 12:00 pm

Verification complexity and volume has always been on the rise, taking significant amount of time, human, and compute resources. There are multiple techniques such as simulation, emulation, FPGA prototyping, formal verification, post-silicon testing, and so on which gain prominence in different situations and at different… Read More


DVCon India

DVCon India
by barun on 08-14-2015 at 12:00 pm

After its successful launch last year, the “Design and Verification Conference & Exhibition India” (DVCon India) will be held on Sept 10 – 11 in Bangalore. The event primarily has two tracks: ESL and DV. The ESL track covers electronic system level (ESL) design and verification, including virtual prototypes of electronic… Read More


Power Management Gets Tricky in IP Driven World

Power Management Gets Tricky in IP Driven World
by Pawan Fangaria on 07-08-2015 at 7:00 pm

Today, an SoC can have multiple instances of an IP and also instances of many different IPs from different vendors. Every instance of an IP can work in a separate mode and requires a dedicated power arrangement which may only be formalized at the implementation stage. The power intent, if specified earlier, will need to be re-generated… Read More


Expansion at Calypto through Real Value Addition in SoC Design

Expansion at Calypto through Real Value Addition in SoC Design
by Pawan Fangaria on 09-22-2014 at 1:00 pm

When we get the notion of expansion of a company, it always provides a positive picture about something good happening to boost that expansion. There can be several reasons for expansion such as merger & acquisition, formation of joint venture or partnership, large customer orders and so on. However, organic expansion which… Read More


Jasper at DVCon and EJUG

Jasper at DVCon and EJUG
by Paul McLellan on 03-13-2014 at 7:05 pm

The Jasper European User Group meeting (EJUG) is coming up in a couple of weeks. It will be held in the Munich Hilton (which I have stayed in many times, the S-bahn from the airport pretty much stops in the basement) on April 2nd.

The schedule for the day is:
9:00 AM – Registration and continental breakfast
9:30 AM – Jasper… Read More


Friday Miscellany: EDAC Mixer, DVCon, DVCon Europe

Friday Miscellany: EDAC Mixer, DVCon, DVCon Europe
by Paul McLellan on 02-28-2014 at 8:31 am

Yesterday evening was EDAC’s first mixer. I assume the first of a regular event. It was held in Mountain View in the old train station which is now the Savvy Cellar wine bar. I had a nice glass of rosé from Provence that reminded me of the years that I lived in the south of France. Some of the money we spent went to charity, to the Mountain… Read More