This comparison of smartphone processors from different companies and fab processes was originally going to be a post, but with the growing information content, I had to put it into an article. Here, due to information availability, Apple, Huawei, and Samsung Exynos processors will get the most coverage, but a few Qualcomm Snapdragon processors will also be included in some comparisons.
The Processes
The processors compared here will be fabbed at Samsung and TSMC, starting from 14/16nm and going down to 7nm EUV versions.
What’s being compared
Die width and die height will be compared among the processors from each of the different companies. Transistor density data (available only for certain processors) will be used for process comparisons.
Smartphone processor die sizes
In Figure 1, the die size trends for the smartphone processors from Samsung, Huawei, and Apple are separately plotted vs. the different processes used.
Figure 1. Die size trends vs. process for Samsung (left), Huawei (center), and Apple (right). Qualcomm is added at far left for die area only.
For Samsung, the introduction of 7LPP enabled a die height reduction. However, unexpectedly, its 91.83 mm2 area does not give the smallest die area among all the processors considered here. Among 7nm processors, the smallest processor area goes to the Snapdragon 855 (73.3 mm2), fabricated on TSMC’s original 7nm process. The Snapdragon 835 was even smaller at 72.3 mm2, but is made on Samsung’s 10nm (LPE) process, with a much lower transistor density. The other 7nm EUV processor, the Huawei Kirin 990 5G made at TSMC, also had enlarged die size (113.3 mm2), but this can be attributed to new features in the processor design [1].
Die width is not trending down with advanced processes. This will be a concern for the use of EUV, as discussed in detail later. With shrinking cell track heights, the impact of illumination rotation will become more significant.
Transistor Density
Transistor density is plotted for Huawei and Apple processors vs. process in Figure 2.
Figure 2. Transistor density vs. process for Huawei (left) and Apple (right).
The biggest surprise here comes from TSMC’s 7nm EUV process NOT giving the highest transistor density. Among the Kirin processors shown, the Kirin 980 gives the highest density (93.1 MTr/mm2) which is higher than the Kirin 990 5G at 90.9 MTr/mm2. The other processor which beat this value is the Snapdragon 855, coming in at 91.4 MTr/mm2.
The highest densities and smallest die sizes so far at 7nm were realized on TSMC’s first 7nm process. The TSMC 7nm process in fact has a shorter high-density track height (240 nm) [2] than Samsung’s 7nm EUV process (243 nm) [3]. The Exynos 990 in fact used the high-performance track height, which is 270 nm. These actually offset the potential benefits of a smaller metal pitch.
Going to 5nm, track height is expected to be reduced, especially with 6-track cells becoming available.
Track height reduction consequences for EUV
Samsung’s 7nm EUV process offers 270 nm (7.5-track) and 243 nm (6.75-track) cell heights. The 5nm continuation of this process also offers a 216 nm (6-track) cell height [4]. The process is considered a continuation because the minimum metal pitch remains at 36 nm. The minimum metal pitch has a strong influence on the EUV process, as it sets a preferred illumination angle (whose sine = 0.1875 to be exact). However, this illumination angle is rotated across the die, up to 18.2 degrees at 13 mm from the center [5]. Since the die width for the Samsung Exynos processors shown in Figure 1 have been in the neighborhood of 10.7 mm, we should consider the effect of a 7.5 degrees (=18.2 degrees x 5.35 mm/13 mm) maximum rotation at the chip edge compared to the center. The effect is not so profound for the 36 nm pitch itself but more so for the track height being the true pitch. The much larger track height as pitch generates a more complex diffraction order spectrum. The phase difference between the 0th and 1st orders is normally not affected significantly by the incident angle “shadow” in the x-direction but the rotation changes this (Figure 3).
Figure 3. The impact of 7.5 degree rotation of illumination for 243 nm (top) and 216 nm (bottom) track heights. For the rotated case, defocus generates a larger range of phase errors across the pupil (different angle tils in x-direction). Thus, images at the die edge go out of focus more easily.
The lines in the 6- or 6.75-track cell will go out of focus more easily at the die edge. The effect is more severe not only as the minimum metal pitch decreases but also as track height decreases, due to larger path differences between consecutive orders at smaller pitches.
What to expect in the future
Now that Huawei’s supply from TSMC has been interrupted, there is a possibility it will rely on a new foundry source within China, such as SMIC [6]. It may try to first replicate the success of the Kirin 980 domestically, as mainland China has not yet reached the ‘7nm’ stage in its technology development. In the meantime, both Apple and Qualcomm continue to be successful in their work with TSMC on the 7nm ‘P’ process. With some reduction in popularity of the Exynos processor series, Samsung’s Exynos processor designs may be swapped for a non-customized ARM core design [7]; it remains to be seen if that can revitalize in-house processor design. Otherwise, Samsung’s phones can still be sold with Qualcomm’s Snapdragon processors exclusively.
References
Processor die size and transistor density information can be found from Techinsights (Exynos 8895, Exynos 9810, Exynos 990, A13, Kirin 990 5G, Snapdragon 835, Snapdragon 865), Anandtech (A9, A10X, Kirin 960, Kirin 980), Chiprebel (Exynos 9820, A11), Wikichip (A12, Kirin 970, Kirin 990 4G, Snapdragon 855).
[3] https://fuse.wikichip.org/news/1479/vlsi-2018-samsungs-2nd-gen-7nm-euv-goes-hvm/
[4] https://fuse.wikichip.org/news/2823/samsung-5-nm-and-4-nm-update/
[5] A. V. Pret et al., Proc. SPIE 10809, 108090A (2018).
[6] https://www.eetasia.com/how-smic-can-keep-up-with-advanced-process-technologies-part-2/
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