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Technology Update With Andrew Faulkner and Jim Lipman of Sidense

Technology Update With Andrew Faulkner and Jim Lipman of Sidense
by Daniel Nenni on 01-23-2017 at 7:00 am

Sidense is an interesting company in a very important market segment. Sidense was founded in 2004 and their 1T-OTP memory macros are now used in hundreds of chips from 180nm to 16nm for code storage, secure encryption keys, analog and sensor trimming and calibration, ID tags, and chip and processor configuration.

If you are designing chips for mobile, automotive, industrial, consumer, or Internet of Things (IoT) you probably already know Sidense but just in case you don’t I was able to catch up with Andrew Faulkner and Jim Lipman for a brief Q&A update on their technology and what we can expect moving forward.

Your one-time programmable memory IP products are based on an antifuse bit cell. Can you briefly explain how the bit cell works?
The antifuse bit cell, when un-programmed, behaves like a capacitor with an insulating SiO[SUB]2[/SUB] layer between a transistor gate and silicon substrate. When programmed, the insulating oxide undergoes a permanent and controlled breakdown and the bit cell behaves like a conducting diode. Unlike an electrical fuse, which is normally conductive or “closed” until a current of sufficient magnitude flows through the fuse and interrupts (blows) the conductive path, an antifuse OTP bit cell is normally non-conductive, representing a “0” logic bit state, until it is programmed to a logic bit state of “1.”

The antifuse OTP bit cell is programmed by applying a sufficiently high-voltage across the gate and substrate of a thin oxide transistor (around 6V for a 2 nm thick oxide, or 30MV/cm) to break down the oxide between gate and substrate. The positive voltage on the transistor’s gate forms an inversion channel in the substrate below the gate, causing a tunneling current to flow through the oxide. The current produces additional traps in the oxide, increasing the current through the oxide and ultimately melting the oxide and forming a permanent conductive channel from gate to substrate. Once programmed, the antifuse bit cell cannot be un-programmed.

Antifuse-based OTP memory operates very reliably over a wide temperature range compared to other types of NVM memory that depend on charge storage to determine the state of the memory’s bit cells. The memory is also highly secure, since it is extremely difficult to read or modify the OTP memory’s contents.

Sidense’s 1T-OTP is one transistor per bit cell – how is this accomplished?
The Sidense bit cell utilizes a unique split channel architecture, 1T-Fuse™, in which the bit cell transistor’s gate overlaps both thick (I/O) and thin (gate) oxide regions. This architecture has been implemented in many foundry and IDM process flows from180nm down to 16nm.

Why have you been able to successfully use a single transistor antifuse-based bit cell for your OTP and what are the advantages over a two-transistor antifuse bit cell?
The 1T-Fuse bit-cell architecture has several advantages over two-transistor antifuse bit cells. Using only one transistor per bit cell results in very small OTP memory arrays that minimally impact the size and cost of the chips in which they are embedded. Since the programming channel is very small and only occurs over the transistor channel, the programming is very robust and reliable. In addition, it is almost impossible to ascertain whether or not a bit cell is programmed, either by physical methods (de-processing or cross sectioning) or by scanning techniques since the bit-cell state does not depend on charge storage, like a flash bit cell.

Sidense has successfully demonstrated 1T-OTP operation down to 16nm FinFET processes. What do you think is the scaling limit for your technology?
Sidense 1T-OTP macros are designed such that the bit-cell programming voltage, which is higher than normal chip operating voltages, does not affect the macro’s peripheral circuitry. The 1T-OTP bit cell architecture has shown good scalability down to 16nm and we don’t expect to run into problems down to 7nm. However as process technology scales, it becomes more difficult to design peripheral circuitry, such as sense amplifiers, to work at the lower voltages of the process. The technology scaling limit may well be set by these circuits rather than by the 1T-OTP bit cell.

What technical challenges are your customers facing with respect to NVM and how does Sidense address them?
We have seen universal acceptance of our OTP across many applications in the Smart Connected Universe, which comprises the mobile computing and communications, IoT, automotive, industrial, medical and wearable market segments. The challenges our customers are seeing in implementing NVM include low-power and low-voltage operation, an expanding need for high temperature operation for automotive and industrial applications and the ever-increasing need for higher security both for data-in-transit and data-at-rest in storage.

Along with the inherent low power and security of the 1T-OTP bit cell, Sidense has developed various circuit techniques to minimize power consumption and enhance OTP IP security. In addition, 1T-OTP is available at more than 17 foundries and almost 60 process variants, including those targeting highly demanding automotive and low-power IoT and mobile applications.

What are the advantages for your customers to design in 1T-OTP compared to other OTP?
I’ve already mentioned 1T-OTP’s broad scalability, from 180nm to 16nm and below, low power and high security attributes. 1T-OTP arrays are available in several BCD, HV and CIS technologies at more than 11 nodes across more than 5 foundries. Compared to other OTP technologies, such as eFuse, 1T-OTP is easy to program and read and is very reliable with retention greater than 10 years at maximum operating temperature and a 100% read duty cycle. Since the state of an antifuse OTP bit cell is not determined by charge storage it is difficult to determine the state of the bit cell, making it inherently secure.

Antifuse-based 1T-OTP does not require any additional masks or process steps and does not require burn-in, again making it a very cost-effective NVM solution. Furthermore, bit-cell programming may be done either by using an external power supply or using an integrated IPS macro, supporting programming at-test or in the field. Once data programmed into OTP is finalized, either for an entire memory array or part of it, conversion to ROM is simple, just by changing one non-critical mask step.

Where does your 1T-OTP fit in with all the new memory technologies (FRAM, MRAM, RRAM, and PCRAM) that are currently under development or in production?
We feel that 1T-OTP serves markets not targeted by the new memory technologies, which are mostly being developed and used as NAND-based flash and DRAM replacements in high-density cache or data storage applications. Many of the new technologies do and will require additional process steps and hence additional cost. For the most part, they are or will be available as separate chips rather than memory IP cores.

What is your take on the IoT market? Does it represent a big opportunity for Sidense?
Absolutely! However, we look at it in a slightly different way than others. Analysts like to talk about killer apps and after the smartphone wave there was a void – without a doubt, IoT has filled that void.

Unfortunately many folks have difficulty getting their heads around IoT and what it is. Is it devices? Is it big data? Is it everything in between? How do we define which market segments it comprises and, more importantly, how do we target them? In our opinion IoT should really be the IoE, the Internet of Everything!

As we discussed earlier we defined the “Smart Connected Universe” that cuts across traditional markets, including automotive, industrial, consumer and others. Devices in the Smart Connected Universe are defined by a few common characteristics: sensing, smarts and connectivity. In fact wherever we see a combination of these characteristics we find a sweet spot for our OTP and eMTP products. Our products are used to store secure keys and trim and calibration parameters, among many other uses. These Smart Connected devices exist as bridges between the analog world that surrounds us and the digital world and with that in mind, sensors are key components. In the IoT ecosystem, sensors are everywhere and so are opportunities for Sidense NVM products.

www.sidense.com