Process shrinks, which have served us well for most of the Moore’s Law journey, are reaching their limits. For switching transistors, the biggest problems of leakage current and gate oxide vulnerability in planar MOSFETs have led the industry to new 3D microstructures such as FinFET. For non-volatile memory, the problem is generally not speed, but endurance and reliability.
In flash memory, smaller cells are more vulnerable to wear when subjected to repeated write operations, and more susceptible to corruption related to noise from nearby cells under programming and other sources. To combat this, 3D V-NAND flash technology has moved to a cylindrical structure, stacking layers of flash cells vertically and relaxing the geometry from 1Xnm class back to 3Xnm class. This effectively packs more cells in the same die footprint, simultaneously relieving the pressure on smaller geometry cells that adversely affects endurance.
Discrete NAND flash is usually fabricated in its own bulk process with dedicated design rules, not a luxury in SoC design (barring stacked 3D substrates, which would still be costly). There have been significant advances in embedded NOR flash at larger geometries, but there are still problems at 1Xnm with respect to write endurance. The dawn of FinFET also brings the challenge of how to cost-effectively fabricate embedded flash structures; lots of research, little commercialization yet.
This makes the reflex to “just grab some flash” a bit problematic for SoC designers adopting FinFET processes right now. Fortunately, many use cases for non-volatile storage can be implemented with one-time programmable (OTP) memory. OTP doesn’t have the same write endurance consideration since each cell is only written once. It fits where the need is for a relatively small but very important space to store encryption keys, tuning parameters, and other information.
To be cost-effective, OTP should live within the confines of the process for the SoC it resides in, ideally requiring no additional process steps for implementation. Overhanging concerns with reliability naturally exist at smaller geometries, and OTP is no exception – but the right approach could manage those issues.
With that in mind, Sidense has announced a very significant breakthrough: a demonstration of OTP cells in TSMC 16nm FinFET. Initial reports are impressive: correct bit-cell operation, using a programming voltage comparable to Sidense 1T OTP in 28nm, with a 10x lower leakage current. Additionally, margins between programmed and unprogrammed cells and post-bake cell stability both appear on target.
How was this, which Sidense believes to be the first working antifuse OTP in FinFET, accomplished? Sidense shared the following diagram (but few details) exclusively with SemiWiki:
This shows how Sidense is leveraging the 3D nature of the FinFET to implement the bit cell, with “no extra steps to the process” quoting an unnamed R&D source. We didn’t get too far with inquiries for specifics, but respect that the technology is still in development and details may be patentable and changing. We do know that TSMC has done extensive work in aligning overlays on FinFETs, and is likely deeply partnered in this Sidense research.
Initial functional and reliability testing of the OTP implementation in 16nm FinFET gave Sidense and TSMC enough confidence to announce the progress, a good sign for SoC designers. This is a development to watch carefully.
FinFETs for your next SoC