Maybe I’ve spent too many years whiffing solder flux fumes and absorbing doses of X-band radiation in anechoic chambers, but I’m a firm believer in the axiom: “Give me enough engineers, and I can get 10 of anything to work right, once.” We have to make this … fit into this … using only this stuff … is what legends are made of.
The trick in the silicon IP business is getting something to work for hundreds of thousands or even millions of cycles, in millions or even billions of deployed units, over years and even decades – that’s less dramatic, but in some ways much harder. There is a huge difference between getting IP that functionally operates in a point design, and delivering IP that customers can embrace in a broad range of designs and applications with utmost confidence.
The breaking news today from Sidense is their SHF 1T-OTP hard macro has completed TSMC9000 on TSMC 28nm processes. SHF has been well-proven and deployed in volume on 40nm, and is in architecture development on even more advanced nodes including 20nm and 16nm FinFET. If these non-volatile memory cells are “just standard CMOS”, what’s the big deal?
As I was researching this, I chuckled after reviewing some reader comments in another outlet regarding a competitive NVM technology in test on TSMC 28nm processes, one in particular questioning if that was “more about luck than any major technical breakthrough.” Interestingly enough, after that first news blurb a couple years ago, I can’t find evidence that technology has yet completed TSMC9000 at 28nm.
The qualification process for hard IP, ensuring yield and reliability in all types of designs, plus the notion of bulletproof data integrity expected from NVM, is a much bigger challenge than just getting it to work. The TSMC9000 IP quality management program is a rigorous set of seven assessments for all types of hard IP, looking at DFM, design margin, and volume production issues. When TSMC puts their stamp on a piece of IP for all its customers, it says something.
There is more engineering in a NVM macro than meets the eye. Sidense SHF supports up to 1Mbit, with support for 16- to 40-bit data including 8-bit ECC protection. It goes beyond just a memory cell, including its own integrated power supply with a charge pump to translate the standard logic voltages into programming voltages, and an RTL implementation of a program controller for designers to use out-of-the-box meeting the sequencing and timing requirements of the memory core.
On the scale of things, an NVM hard macro isn’t billions of transistors with multiple clock domains and complex pipelining – but it is a mixed signal element with parameters that have to be kept strictly in-bounds to achieve the goals. Getting it wrong can kill a design before it leaves the back door, while getting it right can mean years of worry-free operation. Nothing is perfect, but Sidense and TSMC are working together to make sure NVM IP can go anywhere needed.
At DAC in San Francisco next week, Sidense will be explaining more about this and the future for one-time programmable memory in 20nm and 16nm FinFET in live presentations on the show floor (alas, not streamed online to my knowledge). Times and locations are as follows:
ChipEstimate.com (Booth #1533):
Monday, June 2 at 3PM, Tuesday, June 3 at 10:30AM, and Wednesday, June 4 at 11:30AM
TSMC OIP Theatre (Booth #1801):
Wednesday, June 4 at 11:45AM
Be sure to catch one of these sessions if you are at DAC, and tell them I sent you.