Sr Principal Silicon Validation Engineer

Validate DDR, LPDDR and GDDR Cadence test chip silicon for leading edge protocols and advanced nodes. Bringup, characterization and validation of test chips. Work with design team to debug problems and performance issues.  Report results to design teams. Generate test reports suitable for distribution to customers.

Support customer silicon bringups and post silicon queries of our IP and help to debug customer issues with same. Debug issues with customer chips and boards as needed when they are unable to reproduce Cadence test chip results.

Execute special test requests from design team or customers to measure specific parameters or root cause issues.

Recommend and pursue improvements to our test plan and environment to ensure the highest quality IP is produced by Cadence and minimize any silicon issues experienced by our customers.

Position Requirements

• Candidate’s background should include a minimum 7 years of silicon validation experience, preferably in the area of SERDES, DDR or high-speed interface design
• Good understanding of lab equipment and measurement techniques for high speed interfaces.  High speed scopes, probes, spectrum analyzers, BERTs.
• Good understanding of eye diagrams, transmission lines, channel loss etc.
• Knowledge of board and package design
• Knowledge of DDR trainings and memory system operation a plus
• Software proficiency for test scripting, data handling and reporting using scripting languages such as Python, TCL etc.
• Programming skill in C/C++/C# is desirable
• Able to run Verilog test benches and view waves to debug issues
• Communicate with global teams (US, India, China, EU), which work in different time-zones
• Excellent problem-solving skills, good communication skills and ability to work cooperatively in a team environment
• Work with design team to understand requirements, fashion tests and review results
• Mentor Junior Engineers when the project need arises
• BEng, MEng