Senior Staff Physical Design Engineer F/H
Website ArterisIP
Arteris enables engineering and design teams at the world’s most transformative brands to connect and integrate today’s system-on-chips (SoCs) that fuel modern innovation.
If you’ve held a smartphone, driven an electronic car, or powered up a smart TV, you’ve come in contact with what we do at Arteris. Here, the future is quite literally in your hands—and when it isn’t, chances are it is flying overhead in a drone, a satellite, or in the cloud at a datacenter!
The purpose of the role is to ensure the generation and verification of highly configurable IP files for physical implementation tools.
Key Responsibilities:
- Develop and debug flows, constraints on third-party physical implementation tools.
- Define, document, develop and execute verification tests for physical implementation/coverage flows at system level.
- Verify quality of results.
- Triage regressions, debug designs.
- Contribute to improving and refining the process, methodology and choices of physical implementation in line with the evolution of tools and contemporary techniques.
- Coordinates with hardware and software engineers to solve hardware/software compatibility and interface problems.
- Interact with users to define system requirements and/or necessary modifications; provide maintenance information.
Experience Requirements / Qualifications:
- At least 12 years’ experience in digital circuit design and implementation.
- Knowledge of implementation flows such as Cadence and Synopsys
- Expertise in physical implementation debugging.
- Experience of time constraints and their analysis
- Solid knowledge of hardware programming (Verilog system) and software programming (python/TCL type).
- Excellent communication skills.
- Team spirit.
- Able to work in total autonomy
- Fluent English and French
Education Requirements:
- Master’s degree ou Doctorate in engineering or computer science
About Arteris:
Arteris is a leading provider of system IP for the acceleration of system-on-chip (SoC) development across today’s electronic systems. Arteris network-on-chip (NoC) interconnect IP and SoC integration automation technology enable higher product performance with lower power consumption and faster time to market, delivering better SoC economics so its customers can focus on dreaming up what comes next.
With over 250 employees with headquarters in Silicon Valley and offices around the globe, we are a catalyst for SoC innovation so companies ranging from startups to the biggest technology market leaders can effectively create new products with proven connectivity flexibility and ease. Learn more at arteris.com.
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To view the job application please visit www.arteris.com.
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