Senior RTL Engineer

Flex Logix is seeking Inference SoC (System on Chip) and Logic Design Engineers to join our team developing the SoC RTL that controls our Inference SoCs and interfaces; and the “SoftLogic” RTL that controls the execution of the compute kernels of our neural network model operators.

You’ll be working with software engineers, marketing specialists, physical design engineers, verification engineers, & deep learning scientists, to implement the features needed to accelerate the next generation of machine learning algorithms. Must be passionate about being part of an aggressive, venture-backed startup team that is changing chip architecture.  Must be entrepreneurial, innovative problem solver and willing to work hard.
Responsibilities

Be part of our exciting team developing our chips that accelerate the execution of neural networks. The candidate must be able to own major portions of our chips; developing them from concept through execution and silicon bringup support. The candidate must provide technical leadership in solving new and challenging problems that require
coordination with other hardware, software and system engineering teams. The preferred candidate would be able to work in every stage of silicon development: specification, coding, verification, timing closure and post-silicon validation for SoC to deliver microarchitecture and RTL for the full SoC.

Required Experience

• Extensive experience coding Verilog or System Verilog RTL
• Proven track record on delivering micro-architecture and RTL code that works on Silicon and meets timing for high-speed designs
• Experience interfacing with internal and 3rd party IP suppliers
• Experience scripting in Python or Perl
• Experience running Lint, CDC, and other static quality checks
• Experience with starting designs from scratch
• Familiarity with memory architecture in SoCs
• Familiarity with DDR and PCIe standards
• Familiarity with NoC or AXI Crossbars
• BS/MSEE/CE/CS with a minimum of 10 years of experience designing functional units or SOC RTL
• Experience with low power design techniques
• Proven track record of first pass silicon success

Preferred Experience

• Familiarity with C or C++ coding
• BS/MSEE/CE/CS with 15 or more years of experience
• Knowledge of computer architecture, especially in systolic arrays
• Experience with FPGA design and emulation
• Experience with FPGA and ASIC EDA tools