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Senior Hardware Design Verification Engineer

Senior Hardware Design Verification Engineer
by Admin on 10-18-2022 at 3:37 pm

Website ArterisIP

ARTERIS IP is the world leader in SoC and NoC systems, with nearly 200 employees in France and abroad.

Our technology is used by the most innovative electronic systems providers, ranging from AI to automotive, cell phones, IoT, cameras, SSD controllers and servers.

To support our growth, we are looking for a Senior Design Verification Engineer F/H.

In this role, you will join a verification team with a powerful language that blends traditional RTL with cutting-edge software to deliver highly configurable, testable, and high-quality solutions.

Key Responsibilities:

  • Define, document, develop and execute RTL verification test/coverage for extremely parameterized IPs in Python and C++, capable of running on any available RTL simulator (Cadence, Synopsys, etc.).
  • Maintain and improve verification workflow, improve metrics and increase automation.
  • Implement verification components such as BFMs or monsters. such as BFMs or monitors used in verification test benches.

Required Experience / Qualifications:

  • 7+ years of industry experience as a verification engineer.
  • Understanding of hardware RTL design and verification languages (VHDL, Verilog, SystemC, C++, Python, SystemVerilog).
  • Strong experience in the use and development of verification methods and infrastructure (VIPs, UVMs, testbeds, EDA tools).
  • Experience in formal proof verification methodology is a plus
  • Shell scripting
  • Knowledge of interconnect technology is a plus
  • Understanding of hardware communication protocols (AMBA, OCP, others)
  • Good written and oral communication in French and English.
  • Curious, autonomous, rigorous and results-oriented, with a commitment to quality and a thorough approach to work.
  • Proven ability to work well in a team environment

Educational Requirements:

  • Master
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To view the job application please visit www.arteris.com.

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