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Senior Engineer I – ASIC Design

Senior Engineer I – ASIC Design
by Admin on 09-16-2022 at 1:21 pm

Website OpenFive


  • Will be responsible for verification of IP, Block or Subsystem at Soc Level
  • Generate appropriate documentation for verification
  • Responsible for analyse / debug given blocks/tasks in verification
  • Should be able to develop and own the verification environment, verification components developed


  • 3-6 years of experience with a Bachelors/ Master’s degree in the field of Electrical, Electronics or computer engineering
  • Should have good understanding of verification flow, challenges and requirements of functional verification
  • Should have worked on IP level or Block level or SoC level functional verification
  • Skilled in digital verification aspects such as constrained random verification, functional coverage, code coverage, assertions, methodology & philosophy
  • Expert in System Verilog, Verilog and OVM/UVM verification methodology
  • Should have working experience on AMBA interface protocols (AXI, AHB, APB)
  • Knowledge of Verilog/System Verilog, digital simulation and debug is a must
  • Hands on experience on working one or more of the following protocols is a must – UART, I2C, SPI, QSPI, I3C, eMMC, CAN,
  • Hands on experience on working with one or more of following protocols is desired – PCIe, USB, DDR, LPDDR, GBE, SATA
  • Experience with Perl, python or similar scripting language will be helpful
  • Ability to adopt & learn quickly and willingness to proactively take on responsibilities beyond the job description to accomplish team goals
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