Principal Application Engineer
Website Cadence
Job Requirements:
- Master’s degree or above, major in microelectronics, communication, computer, etc., with solid IC digital circuit analysis, understanding and positioning capabilities;
- Familiar with System Verilog and UVM verification methodology;
- Familiar with any script programming in Shell/Perl/Python under LINUX;
- Familiar with one or more of the following verification experience is preferred, Cadence digital verification related EDA software, AMBA (AXI/APB/AHB, etc.) bus protocol, Ethernet/USB/PCIE/I2C/UART and other IP verification experience is preferred;
- Have good communication skills, coordination skills and teamwork awareness, and be able to use English for listening, speaking, reading, writing and communication
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