PHY Logic Design Engineer

In this position you will play a key technical role in developing and verifying PCS RTL for low power, high-speed, Fin- FET SERDES macro to be used in numerous products from high performance data center SoCs to low power nt impact on our products.

Key Qualifications:

• Minimum 1 year of SERDES PCS and PMA RTL development experience
• Expertise in SERDES protocols and PCS architecture such as PCIe, SATA, SAS, Ethernet
• Experience in PHY-level protocol test suite development and integration with link layer controllers
• Experience in high speed FPGA RTL porting, IO mapping, synthesis, timing closure
• Verilog/System Verilog, functional verification skills
• Knowledgeable in advanced RTL digital design methodology
• Working experience with Lint, CDC, Synthesis/P&R/STA, CTS, Xilinx FPGA compiler tools
• Excellent team player and clear communicator
• Ability to operate lab equipment like Oscilloscope etc

Description:

• Contribute to the development and verification of advanced SERDES PCS logic, including clock domains crossing, calibration logic, equalization, adaptation, auto-negotiation, BER eye monitor, etc
• Develop micro-architecture and test-chip/test-system specifications
• Develop Verilog test benches, diagnostics, and product test flow procedures
• Work closely with the PMA design team
• Document the design for internal and external purposes, including maintaining PHY user guides
• Interface with customers and assist in integrating the Serdes IP
• Participate in all test chip and bring up activities
• Help improve RTL design and verification methodology

Education: BS required / MS or PhD preferred in electrical engineering or related field

We are an equal opportunity employer and value diversity in our workforce. All employment decisions are made on the basis of qualifications, ability, and business requirements.