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Lead Test Engineer

Lead Test Engineer
by Admin on 10-05-2023 at 5:02 pm

Website Cadence

Validate DDR, LPDDR and GDDR Cadence test chip silicon for leading edge protocols and advanced nodes. Bringup, characterization and validation of test chips. Work with design team to debug problems and performance issues. Report results to design teams. Generate test reports.

Position Requirements

  • Candidate’s background should include a minimum 1 year of silicon test and validation experience
  • Good understanding of lab equipment and measurement techniques for high speed interfaces.  High speed scopes, probes, spectrum analyzers, BERTs.
  • Software proficiency for test scripting, data handling and reporting using scripting languages such as Python, TCL etc.
  • Communicate with global teams (US, India, China, EU), which work in different time-zones
  • Excellent problem-solving skills, good communication skills and ability to work cooperatively in a team environment
  • Work with design team to understand requirements, fashion tests and review results
  • BEng, MEng

The annual salary range for California is $108,500 to $201,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

Apply for job

To view the job application please visit cadence.wd1.myworkdayjobs.com.

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