Internship: UVM verification

6 months, based in Sophia-Antipolis, France.

Job description

You will have to architect, develop and verify a versatile verification environment fully scriptable for Menta’s eFPGA IP. The tasks are:

• Set-up the verification environment (UVM)

• Develop the integrated bench in SystemVerilog

• Automate test procedures and perform regular non-regression tests

• Realize reports automation

• Maintain the environment to support miscellaneous architectures and features

Required skills and experience

• Internship for MS in Electrical Enigineering / Electronics

• Knowledge of logic design principles

• Practical experience of the UVM methodology

• Knowledge of harware description languages Verilog, System Verilog and VHDL

• Experience with simulators and weveform debugging tools

• Experience using a scripting language such as perl/Python/bash

• Good knowledge of unix/linux command lines (bash) and Makefiles

• Basic knowledge of versioning tools (git) is a plus

• Good written and spoken English is advised