Intern (Technical-Engineering)
Website Synopsys
As an intern at Synopsys, you will have the opportunity to gain hands-on experience while working alongside industry professionals. You will build and refine skills relevant to your major and future career. This internship provides an excellent opportunity to learn the ASIC Digital Design Process and gain a working understanding of Synopsys implementation tools and flow.
- You are pursuing or have a strong interest in VSLI Design
- Strong fundamentals of Electrical Circuit Design and analysis
Skill Requirements:
- Verilog/System Verilog
- VHDL
- C/C++
- Python/tcl/perl
- Familiar with Unix/Linux environment
- Self-motivated
- Team player
Education Qualifications:
- All interns must be currently enrolled in an accredited educational institution.
- Seeking Master students
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